Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
READ_BLOCK
The READ_BLOCK cycle is generated on read misses. The B-Cache controller reads
the addressed block from memory and supplies it, 128 bits at a time, to the 21064 via
the data bus. The B-Cache location that missed will be victimized and then updated
with the new cache entry.
WRITE_BLOCK
The WRITE_BLOCK cycle is generated on write misses, and on writes to shared
blocks. The B-Cache controller pulls the write data, 128 bits at a time, from the
21064 via the data bus, and writes the valid longwords to memory.
LDxL
The LDxL cycle is generated by the LDLL and LDQL instructions. The cycle works
just like a READ_BLOCK, although the B-Cache is not probed by the processor. The
B-Cache controller performs the B-Cache probe and if the reference is to cacheable
address space, the address is latched into the Address Lock Register.
STxC
The STxC cycle is generated by the STLC and STQC instructions. The cycle works
just like a WRITE_BLOCK, although the B-Cache is not probed by the processor. The
B-Cache controller performs the B-Cache probe and then the cycle is acknowledged
with the completion status. The following tables show the encodings of the cycle
request and acknowledge signals between DECchip 21064 and the interface ASICs.
Table 59: Cycle Request
cReq_h[2] cReq_h[1] Creq_h[0] Type
L L L IDLE
L L H BARRIER
L H L FETCH
L H H FETCH_M
H L L READ_BLOCK
H L H WRITE_BLOCK
H H L LDL_L/LDQ_L
H H H STL_C/STQ_C
144 CPU Module Transactions