Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 54 (Cont.): BIU_CTL Field Description
Field Description
7:4 BC_RD_SPD [ write-only ]
Backup (external) cache read speed. This field indicates to the bus interface unit the read
access time of the RAMs used to implement the off-chip external cache, measured in CPU
cycles. This field should be written with a value equal to one less the read access time of
the external cache RAMs.
Access times for reads must be in the range 16..3 CPU cycles, which means the values for
the BC_RD_SPD field are in the range of 15..2.
BC_RD_SPD are not initialized on reset and must be explicitly written before enabling the
external cache.
3 BC_FHIT [ write-only ]
Backup cache force hit. (This cache is external to the 21064 chip.) When this bit and
2
BC_EN are set, all pin bus READ_BLOCK and WRITE_BLOCK transactions are forced to
hit in the backup cache. Tag and tag control parity are ignored when the BIU operates in
this mode. BC_EN takes precedence over BC_FHIT. When BC_EN is clear and BC_FHIT
is set, no tag probes occur and external requests are directed to the CREQ_H pins.
Note that the BC_PA_DIS field takes precedence over the BC_FHIT bit.
OE [ write-only ]
Output enable - When this bit is set, the 21064 CHP chip does not assert its chip enable
pins during RAM write cycles, thus enabling these pins to be connected to the output enable
pins of the cache RAMs.
1 EDC [ write-only ]
Error detection and correction. When this bit is set, the 21064 CPU chip generates/expects
EDC on the CHECK_H pins. When this bit is clear the CPU chip generates/expects parity
on four of the CHECK_H pins.
0 BC_ENA [ write-only ]
External cache enable. When clear, this bit disables the external cache. When the external
cache is disabled, the BIU does not probe the external cache tag store for read and write
references; it initiates a request on CREQ_H immediately.
Table 56: BIU_CTL Initialization Values
Module Description Init Vaule Note
Sable B2020-AA E30006447 1MB 5 tick cache, 2 cycle write strobe
Sable B2024-AA E5000E567 4MB 6/7 tick cache, 3 cycle write strobe
If an error occurs (either non-existent or bad checksum) when reading the CPU’s IIC
bus EEPROM the following defaults for will be used.
140 Functions located elsewhere on the CPU module