Sable CPU Module Specification
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Sable CPU Module Specification

Sable CPU Module Specification Sable CPU Module Specification

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Copyright © 1993 Digital Equipment Corporation. NOTE The control flags in location ^xFE only have meaning if is a Serial Console is attached to the IIC bus on the system. If no Serial Console is present these flags are treated as set i.e. always run tests and auto-unload on powerup/reset. Table 54: BIU_CTL Field Description Field Description 63:44 MBZ [ write-only ] 43 BC_BURST_ALL [ write-only ] 42:40 BC_BURST_SPD [ write-only ] 39 MBZ [ write-only ] 38 SYS_WRAP [ write-only ] 37 BYTE_PARITY [ write-only ] 36 BAD_DP [ write-only ] Bad Data Parity - When set, BAD_DP causes the 21064 CPU to invert the value placed on bits , , and of the check_h field during off-chip writes. This produces bad parity when the 21064 CPU is in parity mode, and bad check bit codes when the CPU is in EDC mode. 35:32 BC_PA_DIS [ write-only ] Backup cache physical address disable - This 4-bit field may be used to prevent the CPU chip from using the external cache to service reads and writes based on the quadrant of physical address space which they reference. The table below shows the correspondence between this bit field and the physical address space. When a read or write reference is presented to the bus interface unit (BIU), the values of BC_PA_DIS, BC_ENA, and physical address bits together determine whether or not to try using the external cache to satisfy the reference. If the external cache is not to be used for a given reference, the bus interface unit does not probe the tag store and makes the appropriate system request immediately. The value of BC_PA_DIS has no impact on which portions of the physical address space may be cached in the primary caches. System components control this through the DRACK field of the pin bus. BC_PA_DIS is not initialized by a reset. BIU_CTL bit Physical Address [32] PA[33..32] = 0 [33] PA[33..32] = 1 [34] PA[33..32] = 2 [35] PA[33..32] = 3 31 BAD_TCP [ write-only ] BAD Tag Control Parity - When set, BAD_TCP causes the 21064 CPU to write bad parity into the tag control RAM whenever it does a fast external RAM write. 138 Functions located elsewhere on the CPU module

Table 54 (Cont.): BIU_CTL Field Description Field Description Copyright © 1993 Digital Equipment Corporation. 30:28 BC_SIZE [ write-only ] Backup Cache Size - This field is used to indicate the size of the external cache. BC_SIZE is not initialized by a reset and must be explicitly written before enabling the backup cache. BC_SIZE Size 0 0 0 128 Kbytes 0 0 1 256 Kbytes 0 1 0 RESERVED 0 1 1 1 Mbytes 1 0 0 2 Mbytes 1 0 1 4 Mbytes 1 1 0 8 Mbytes 27:13 BC_WE_CTL[15:1] [ write-only ] Backup Cache Write Enable Control. This field controls the timing of the write enable and chip enable pins during writes into the data and tag control RAMs. It consists of 15 bits, where each bit determines the value placed on the write enable and chip enable pins during a given CPU cycle of the RAM write access. When a given bit of BC_WE_CTL is set, the write enable and chip enable pins are asserted during the corresponding CPU cycle of the RAM access. BC_WE_CTL (bit 13 in BIU_ CTL) corresponds to the second cycle of the write access, BC_WE_CTL (bit 14 in BIU_ CTL) to the third CPU cycle, and so on. The write enable pins are never asserted in the first CPU cycle of a RAM write access. Unused bits in the BC_WE_CTL field must be written with 0s. BC_WE_CTL is not initialized on reset and must be explicitly written before enabling the external backup cache. 12 DELAY_WDATA [ write-only ] DELAY_DATA 11:8 BC_WR_SPD [ write-only ] Backup cache write speed. This field indicates to the bus interface unit the write cycle time of the RAMs used to implement the off-chip external cache, (Backup cache on the CPU module), measured in CPU cycles. It should be written with a value equal to one less the write cycle time of the external cache RAMs. Access times for writes must be in the range 16..2 CPU cycles, which means the values for the BC_WR_SPD field are in the range of 15..1. BC_WR_SPD is not initialized on reset and must be explicitly written before enabling the external cache. Functions located elsewhere on the CPU module 139

Table 54 (Cont.): BIU_CTL Field Description<br />

Field Description<br />

Copyright © 1993 Digital Equipment Corporation.<br />

30:28 BC_SIZE [ write-only ]<br />

Backup Cache Size - This field is used to indicate the size of the external cache. BC_SIZE<br />

is not initialized by a reset and must be explicitly written before enabling the backup cache.<br />

BC_SIZE Size<br />

0 0 0 128 Kbytes<br />

0 0 1 256 Kbytes<br />

0 1 0 RESERVED<br />

0 1 1 1 Mbytes<br />

1 0 0 2 Mbytes<br />

1 0 1 4 Mbytes<br />

1 1 0 8 Mbytes<br />

27:13 BC_WE_CTL[15:1] [ write-only ]<br />

Backup Cache Write Enable Control. This field controls the timing of the write enable and<br />

chip enable pins during writes into the data and tag control RAMs. It consists of 15 bits,<br />

where each bit determines the value placed on the write enable and chip enable pins during<br />

a given <strong>CPU</strong> cycle of the RAM write access.<br />

When a given bit of BC_WE_CTL is set, the write enable and chip enable pins are asserted<br />

during the corresponding <strong>CPU</strong> cycle of the RAM access. BC_WE_CTL (bit 13 in BIU_<br />

CTL) corresponds to the second cycle of the write access, BC_WE_CTL (bit 14 in BIU_<br />

CTL) to the third <strong>CPU</strong> cycle, and so on. The write enable pins are never asserted in the<br />

first <strong>CPU</strong> cycle of a RAM write access.<br />

Unused bits in the BC_WE_CTL field must be written with 0s.<br />

BC_WE_CTL is not initialized on reset and must be explicitly written before enabling the<br />

external backup cache.<br />

12 DELAY_WDATA [ write-only ]<br />

DELAY_DATA<br />

11:8 BC_WR_SPD [ write-only ]<br />

Backup cache write speed. This field indicates to the bus interface unit the write cycle time<br />

of the RAMs used to implement the off-chip external cache, (Backup cache on the <strong>CPU</strong><br />

module), measured in <strong>CPU</strong> cycles. It should be written with a value equal to one less the<br />

write cycle time of the external cache RAMs.<br />

Access times for writes must be in the range 16..2 <strong>CPU</strong> cycles, which means the values for<br />

the BC_WR_SPD field are in the range of 15..1.<br />

BC_WR_SPD is not initialized on reset and must be explicitly written before enabling the<br />

external cache.<br />

Functions located elsewhere on the <strong>CPU</strong> module 139

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