Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
There are special arbitor modes of operation where the bus priority algorithm is
modifed. In particular, a CPU or I/O mode can gaurantee exclusive ownership of the
system bus by keeping its appropriate request line aserted. Normal arbitration protocol
requires that the request signal deassert for at least one cycle before reasserting
if exclusive bus ownership is not required. This deassertion and reassertion can occur
during an existing cycle so that back-to-back arbitration is still granted to the
requesting node if there are no other requesters for the system bus.
Both CPU and I/O modes may be allowed this mode of operation, however DECchip
21064 and DECchip 21064-A275 implementations will have this feature disabled for
CPU requests. Only I/O will be allowed to enter the Exclusive access mode.
During normal operation for Sable DECchip 21064 and DECchip 21064-A275 systems,
the Sable bus arbitor will monitor bus activity and insert a single idle cycle
after the fifth consecutive back-to-back transaction. This feature gaurantees that a
CPU is never locked out of its own backup cache and is gauranteed to make progress.
There is also a debug arbitration feature available by writing to bit in the System
Bus Control Register (CSR6–CBCTL) which forces the injection of two idle bus cycles
between every bus transaction.
Table 52: Sable Arbitration Latency
Node Latency (Bus Cycles)
CPU0
CPU1
CPU2
CPU3
Latency From EV_Req to Cobra Bus cycle 0
3-4
4-5
4-5
4-5
Node Latency (Bus Cyles)
IO0(T2)
IO1(XIO)
Latency From I/O req to Cobra Bus cycle 0
4.15 System-bus CRESET L Generation
3
3
System-bus CRESET L is generated on Cobra CPU 0 module. It is asserted when
either async_reset from the Standard I/O module is asserted, the System-bus or the
21064 oscillator on CPU 0 stop, or the 3.3V supply on CPU 0 goes under voltage.
The clock detect circuits on the CPU module will guarantee that the oscillator generating
the clocks for the module have been running for at least 20ms. This is to allow
enough time to for the oscillators to stabilize.
136 Functions located elsewhere on the CPU module