Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. 4. The processor type commander requests have biased after the idle Cobra-bus. For example, If CPU0, CPU1, CPU2, CPU3,IO0(T2), and IO1(XIO) are all requesting the Cobra-bus simultaneously after the system reset event and each node needs the Cobra-bus for two transaction cycles, then the granting of the bus will follow the order listed below. Note that CPU0 commander node has won the first Cobra-bus mastership because the processor type commander requests have a bias in arbitration. An illustration of the granting order is shown in Figure 58. 1. CPU0 : algorithm rule-4 2. IO0(T2) : algorithm rule-3 3. CPU1 : algorithm rule-3, rule-1 4. IO1(XIO) : algorithm rule-3, rule-2 5. CPU2 : algorithm rule-3, rule-1 6. IO0(T2) : algorithm rule-3, rule-2 7. CPU3 : algorithm rule-3, rule-1 8. IO1(XIO) : algorithm rule-3, rule-2 9. CPU0 : algorithm rule-3, rule-1 10. CPU1 : algorithm rule-1 11. CPU2 : algorithm rule-1 12. CPU3 : algorithm rule-1 134 Functions located elsewhere on the CPU module
Figure 58: Granting Order rule 4 CPU CPU CPU CPU 0 1 2 3 1 9 rules 3 + 1 rule 1 3 10 rules 3 + 1 rule 1 5 11 rules 3 + 1 rule 1 rules 3 + 1 7 12 Copyright © 1993 Digital Equipment Corporation. rule 3 rules 3 + 2 2 6 rules 3 + 2 IO IO 8 0 (T2) 1 (XIO) rules 3 + 2 4 [yuryan.cpu]granting_order.doc PS @ 70% Functions located elsewhere on the CPU module 135
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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Page 99 and 100: CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Page 103 and 104: Figure 41: B-Cache Control Register
Page 105 and 106: Table 28 (Cont.): B-Cache Control R
Page 107 and 108: Table 28 (Cont.): B-Cache Control R
Page 121 and 122: 4.3.1 Duplicate Tag Error Register
Page 123 and 124: 4.5 Lack of Cache Block Prefetch Co
Page 125 and 126: Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
Page 131 and 132: Table 38 (Cont.): System-bus Error
Page 133 and 134: 4.7.3 System-bus Error Address Low
Page 137 and 138: 4.8 Multiprocessor Configuration CS
Page 139 and 140: 4.9 System Interrupt Clear Register
Page 141 and 142: 4.10 Address Lock Register - CSR13
Page 143 and 144: 4.11 Miss Address Register - CSR14
Page 145 and 146: Table 46 (Cont.): C4 Revision Regis
Page 147 and 148: Table 48 (Cont.): Interval Timer In
Page 149: Table 50: D-bus Microcontroller Clo
Page 155 and 156: Table 54 (Cont.): BIU_CTL Field Des
Page 157 and 158: Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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