Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
4. The processor type commander requests have biased after the idle Cobra-bus.
For example,
If CPU0, CPU1, CPU2, CPU3,IO0(T2), and IO1(XIO) are all requesting the Cobra-bus
simultaneously after the system reset event and each node needs the Cobra-bus for
two transaction cycles, then the granting of the bus will follow the order listed below.
Note that CPU0 commander node has won the first Cobra-bus mastership because
the processor type commander requests have a bias in arbitration. An illustration of
the granting order is shown in Figure 58.
1. CPU0 : algorithm rule-4
2. IO0(T2) : algorithm rule-3
3. CPU1 : algorithm rule-3, rule-1
4. IO1(XIO) : algorithm rule-3, rule-2
5. CPU2 : algorithm rule-3, rule-1
6. IO0(T2) : algorithm rule-3, rule-2
7. CPU3 : algorithm rule-3, rule-1
8. IO1(XIO) : algorithm rule-3, rule-2
9. CPU0 : algorithm rule-3, rule-1
10. CPU1 : algorithm rule-1
11. CPU2 : algorithm rule-1
12. CPU3 : algorithm rule-1
134 Functions located elsewhere on the CPU module