Sable CPU Module Specification

More documents

Recommendations

Info

$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

xiv 73 B-Cache Tag Control or Tag Store Errors ......................... 181 74 B-Cache Data Correctable Errors ............................... 183 75 Uncorrectable Data Store Error Severity Matrix . . .................. 184 76 B-Cache Uncorrectable Errors .................................. 185 77 C/A Parity Errors ........................................... 187 78 Data Parity Errors .......................................... 187 79 LDQ Data Format Description ................................. 191 80 Kernel Survivability Matrix ................................... 195 81 MCA240 J5 ................................................ 197 82 MCA44 J1 ................................................. 200 83 MCA44 J3 ................................................. 201 84 CPU Power Requirements . . ................................... 203 85 System bus AC and DC Characteristics .......................... 208 86 HW_MFPR and HW_MTPR Format Description . . .................. 225 87 IPR Access ................................................. 225 88 HW_LD and HW_ST Format Description ......................... 227 89 The HW_REI Format Description ............................... 228 90 PAL Entry Points ........................................... 229 91 D-stream Error PAL Entry Points ............................... 231 92 IPR Reset State . . ........................................... 235 93 Revision History . ........................................... 243
Preface Scope and Organization of this Specification This specification describes the operation of the Sable CPU. It contains an overview of the system, the CPU module interfaces to the memory and I/O modules and descriptions of transactions, addressing, signals, interface registers, and electrical specifications. In addition, the specification contains discussions of error handling, interrupts, and initialization as well as a description of the PALcode required to provide ALPHA SRM conformance. Related Documents The following documents are related to or were used in the preparation of this document: • 21064 Processor Specification • Alpha System Reference Manual Version 5.0 • Cobra System Bus Specification • Sable System Spec • Sable I/O module Specification • Sable Motherboard Specification • Sable Memory Specification • Sable PFMS Terminology and Conventions Ranges and Extents Ranges are specified by a pair of numbers separated by a ‘‘..’’ and are inclusive, for example, a range of integers 0..4 includes the integers 0,1,2,3,and 4. Extents are specified by a pair of numbers in angle brackets separated by a colon and are inclusive, for example, bits specify an extent of bits including bits 7, 6, 5, 4, and 3. Conventions Physical addresses are expressed as nine hexadecimal digits punctuated with periods every four digits for readability. (for example, 2.0800.0040(hex)) All numbers are decimal unless otherwise indicated. Where there is ambiguity, numbers other than decimal are indicated with the name of the base following the number in parentheses, for example, FF (hex). Preface v
Page 1 and 2: Sable CPU Module Specification This
Page 3 and 4: CONTENTS Preface ..................
Page 5 and 6: 3.9.6 Data Cache Address Register (
Page 7 and 8: 7.1.1 Exception Handling ..........
Page 9 and 10: 11.4 Environmental Specifications -
Page 11 and 12: 25 MM_CSR .........................
Page 13: 27 Base Addresses for CSRs . . . ..
Page 17 and 18: Copyright © 1993 Digital Equipment
Page 19 and 20: CHAPTER 1 CPU MODULE COMPONENTS AND
Page 23 and 24: 1.2 The Alpha AXP Architecture Copy
Page 65 and 66:
Copyright © 1993 Digital Equipment
Page 67 and 68:
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
Page 101 and 102:
Page 103 and 104:
Figure 41: B-Cache Control Register
Page 105 and 106:
Table 28 (Cont.): B-Cache Control R
Page 107 and 108:
Table 28 (Cont.): B-Cache Control R
Page 109 and 110:
Page 111 and 112:
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
4.3.1 Duplicate Tag Error Register
Page 123 and 124:
4.5 Lack of Cache Block Prefetch Co
Page 125 and 126:
Table 37: System-bus Control Regist
Page 127 and 128:
4.7.2 System-bus Error Register - C
Page 129 and 130:
Table 38: System-bus Error Register
Page 131 and 132:
Table 38 (Cont.): System-bus Error
Page 133 and 134:
4.7.3 System-bus Error Address Low
Page 135 and 136:
Page 137 and 138:
4.8 Multiprocessor Configuration CS
Page 139 and 140:
4.9 System Interrupt Clear Register
Page 141 and 142:
4.10 Address Lock Register - CSR13
Page 143 and 144:
4.11 Miss Address Register - CSR14
Page 145 and 146:
Table 46 (Cont.): C4 Revision Regis
Page 147 and 148:
Table 48 (Cont.): Interval Timer In
Page 149 and 150:
Table 50: D-bus Microcontroller Clo
Page 151 and 152:
Figure 58: Granting Order rule 4 CP
Page 153 and 154:
Page 155 and 156:
Table 54 (Cont.): BIU_CTL Field Des
Page 157 and 158:
Table 57: CPU EEPROM Defaults Locat
Page 159 and 160:
Page 161 and 162:
Page 163 and 164:
Page 165 and 166:
Page 167 and 168:
Page 169 and 170:
Page 171 and 172:
Page 173 and 174:
Page 175 and 176:
Page 177 and 178:
Page 179 and 180:
Page 181 and 182:
Page 183 and 184:
Page 185 and 186:
Page 187 and 188:
Page 189 and 190:
Page 191 and 192:
Page 193 and 194:
Page 195 and 196:
Page 197 and 198:
Page 199 and 200:
Page 201 and 202:
Page 203 and 204:
Page 205 and 206:
Page 207 and 208:
Page 209 and 210:
Page 211 and 212:
CHAPTER 11 PHYSICAL AND ELECTRICAL
Page 213 and 214:
Table 81 (Cont.): MCA240 J5 SIDE 1
Page 215 and 216:
Table 82 (Cont.): MCA44 J1 Side 1 S
Page 217 and 218:
11.3 CPU Module Max DC Power Requir
Page 219 and 220:
Page 221 and 222:
Figure 68: module clocks Cobra - b
Page 223 and 224:
Table 85 (Cont.): System bus AC and
Page 225 and 226:
APPENDIX A ALPHA ARCHITECTURE OPTIO
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Page 235 and 236:
Page 237 and 238:
Page 239 and 240:
Page 241 and 242:
Page 243 and 244:
Page 245 and 246:
Page 247 and 248:
Page 249 and 250:
Page 251 and 252:
Page 253 and 254:
Page 255 and 256:
Page 257 and 258:
INDEX 21064 IEEE floating point con
Page 259 and 260:
Icache, 59 ICCSR, 19 IEEE Floating
Page 261:
STQC cycle, 144 STxC cycle, 144 STx
show all

Sable CPU Module Specification

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?