Sable CPU Module Specification
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Sable CPU Module Specification

Sable CPU Module Specification Sable CPU Module Specification

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Copyright © 1993 Digital Equipment Corporation. Table 47: CSR Space CSR Mnemonic CPU0 CPU1 CPU2 CPU3 0 BCC 3.8000.0000 3.8100.0000 3.8200.0000 3.8300.0000 1 BCCE 3.8000.0020 3.8100.0020 3.8200.0020 3.8300.0020 2 BCCEA 3.8000.0040 3.8100.0040 3.8200.0040 3.8300.0040 3 BCUE 3.8000.0060 3.8100.0060 3.8200.0060 3.8300.0060 4 BCUEA 3.8000.0080 3.8100.0080 3.8200.0080 3.8300.0080 5 DTER 3.8000.00A0 3.8100.00A0 3.8200.00A0 3.8300.00A0 6 CBCTL 3.8000.00C0 3.8100.00C0 3.8200.00C0 3.8300.00C0 7 CBE 3.8000.00E0 3.8100.00E0 3.8200.00E0 3.8300.00E0 8 CBEAL 3.8000.0100 3.8100.0100 3.8200.0100 3.8300.0100 9 CBEAH 3.8000.0120 3.8100.0120 3.8200.0120 3.8300.0120 10 PMBX 3.8000.0140 3.8100.0140 3.8200.0140 3.8300.0140 11 IPIR 3.8000.0160 3.8100.0160 3.8200.0160 3.8300.0160 12 SIC 3.8000.0180 3.8100.0180 3.8200.0180 3.8300.0180 13 ADLK 3.8000.01A0 3.8100.01A0 3.8200.01A0 3.8300.01A0 14 MADRL 3.8000.01C0 3.8100.01C0 3.8200.01C0 3.8300.01C0 15 CRR 3.8000.01E0 3.8100.01E0 3.8200.01E0 3.8300.01E0 4.12 Interval Timer The Sable CPU module receives the signal CINT_TIM H off the system bus and generates and interval timer interrupt to the processor. The interface gate arrays require that the source of the CINT_TIM H have a duty cycle of approximately 50%, and that the frequency of CINT_TIM H be twice that of the required interval timer interrupt passed to the processor. Interval timer interrupts are intentionally staggered in a multiprocessing system so that the different processors see the interval timer interrupt at different times. The following table shows the order that interrupts are delivered to the different CPU modules: Table 48: Interval Timer Interrupt Generation CINT_TIM H Interrupted CPU rising edge CPU 0 falling edge CPU 1 rising edge CPU 2 falling edge CPU 3 rising edge CPU 0 falling edge CPU 1 130 Functions located elsewhere on the CPU module

Table 48 (Cont.): Interval Timer Interrupt Generation CINT_TIM H etc... Interrupted CPU Copyright © 1993 Digital Equipment Corporation. Note that for an interval timer frequency of 976.5625 microseconds, the source should actually be programmed for twice that frequency. 4.13 D-bus A serial ROM of size 16KB is located on the CPU module and is used to supply the processor with its power-up code. This ROM pattern is loaded into 8K of the 21064 processor’s internal ICache under the control of the processor after power-up reset only. The data loaded consists of each cache blocks’ tag, ASN, ASM, valid, branch history, and 8 longwords of data. This data is loaded in sequential order starting with block zero and ending with block 255. The order in which bits within each block are serially loaded is shown in Figure 57. Figure 57: The 21064 Serial Load Data Format BH LW7 LW5 LW3 LW1 V ASN TAG LW6 LW4 LW2 LW0 Shift direction ASM Bits within each field are arranded such that high−order bits are on the left. The table also shows the values which must loaded into each cache block’s tag and control bits. An extension serial ROM of up to 16KB will be automatically multiplexed onto the D-bus after the initial 16KB is read into the processor. The software system is able to load this ROM into the data cache of the processor (or the B-Cache to execute) it by alternately toggling the TMT bit in the SL_XMIT register of the processor, and reading the RCV bit of the processors SL_RCV register. There is no need to read the unused portion of the initial serial ROM under program control. The extension serial ROM can be read immediately. The first extension ROM data bit is present in the SL_RCV register 500ns after the completion of the initial serial ROM load and then 500ns after every subsequent 0 to 1 transition of the TMT bit in the SL_XMIT register. The TMT bit should not be toggled from 1 to 0 nor 0 to 1 with a delay smaller than 500ns between transitions. This ROM can only be read once, after a hard system reset. Functions located elsewhere on the CPU module 131

Copyright © 1993 Digital Equipment Corporation.<br />

Table 47: CSR Space<br />

CSR Mnemonic <strong>CPU</strong>0 <strong>CPU</strong>1 <strong>CPU</strong>2 <strong>CPU</strong>3<br />

0 BCC 3.8000.0000 3.8100.0000 3.8200.0000 3.8300.0000<br />

1 BCCE 3.8000.0020 3.8100.0020 3.8200.0020 3.8300.0020<br />

2 BCCEA 3.8000.0040 3.8100.0040 3.8200.0040 3.8300.0040<br />

3 BCUE 3.8000.0060 3.8100.0060 3.8200.0060 3.8300.0060<br />

4 BCUEA 3.8000.0080 3.8100.0080 3.8200.0080 3.8300.0080<br />

5 DTER 3.8000.00A0 3.8100.00A0 3.8200.00A0 3.8300.00A0<br />

6 CBCTL 3.8000.00C0 3.8100.00C0 3.8200.00C0 3.8300.00C0<br />

7 CBE 3.8000.00E0 3.8100.00E0 3.8200.00E0 3.8300.00E0<br />

8 CBEAL 3.8000.0100 3.8100.0100 3.8200.0100 3.8300.0100<br />

9 CBEAH 3.8000.0120 3.8100.0120 3.8200.0120 3.8300.0120<br />

10 PMBX 3.8000.0140 3.8100.0140 3.8200.0140 3.8300.0140<br />

11 IPIR 3.8000.0160 3.8100.0160 3.8200.0160 3.8300.0160<br />

12 SIC 3.8000.0180 3.8100.0180 3.8200.0180 3.8300.0180<br />

13 ADLK 3.8000.01A0 3.8100.01A0 3.8200.01A0 3.8300.01A0<br />

14 MADRL 3.8000.01C0 3.8100.01C0 3.8200.01C0 3.8300.01C0<br />

15 CRR 3.8000.01E0 3.8100.01E0 3.8200.01E0 3.8300.01E0<br />

4.12 Interval Timer<br />

The <strong>Sable</strong> <strong>CPU</strong> module receives the signal CINT_TIM H off the system bus and<br />

generates and interval timer interrupt to the processor. The interface gate arrays<br />

require that the source of the CINT_TIM H have a duty cycle of approximately 50%,<br />

and that the frequency of CINT_TIM H be twice that of the required interval timer<br />

interrupt passed to the processor.<br />

Interval timer interrupts are intentionally staggered in a multiprocessing system so<br />

that the different processors see the interval timer interrupt at different times. The<br />

following table shows the order that interrupts are delivered to the different <strong>CPU</strong><br />

modules:<br />

Table 48: Interval Timer Interrupt Generation<br />

CINT_TIM H<br />

Interrupted<br />

<strong>CPU</strong><br />

rising edge <strong>CPU</strong> 0<br />

falling edge <strong>CPU</strong> 1<br />

rising edge <strong>CPU</strong> 2<br />

falling edge <strong>CPU</strong> 3<br />

rising edge <strong>CPU</strong> 0<br />

falling edge <strong>CPU</strong> 1<br />

130 Functions located elsewhere on the <strong>CPU</strong> module

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