Sable CPU Module Specification

Table 46 (Cont.): C4 Revision Register Description
Field Description
Copyright © 1993 Digital Equipment Corporation.
35:32 Revision [ read-only ]
The state of these bits must match bits
31 Disable CPU Node [ read/write ]
Cleared on power-up. When set, this bit disables a CPU from probing the backup cache and
participating in system bus transactions. The state of this bit must match bit .
24 Forced Dcache Inv [ read/write ]
Cleared on power-up. When set forces all CBUS writes to invalidate the processors d-cache
regardless of whether it hits in the duplicate tag. This is a feature for diagnostics. The state of
this bit must match bit
17 Enable I/O Retry [ read/write ]
Cleared on power-up. When this bit is set, read and writes to I/O space will be re-tried if signaled
by the I/O module. If clear, the retry signaling mechanism is treated as an error and logged in
CSR-7 (CBE). The state of this bit must match bit
15 Disable Duplicate Tag Parity Check [ read/write ]
Cleared on power-up. When set, disables parity checking logic for the duplicate tag in the
interface ASICS. When clear, duplicate tag parity checking may be enabled or disabled as programmed
by CSR0 bit 2. This bit only controls the EVEN slice asic.
14:8 Cache Interface Speed Bits [ read/write ]
Cleared on power-up. When set, each bit corresponds to a control signal which can be slightly
shifted in time, thereby allowing greater flexibility in operating speed combinations between processor
and system bus. The state of this bit must match bit
4 CPU Mode [ read-only ]
Indicates the pin bus mode for which the ASIC has autoconfigured. This is a read-only field.
• 0 - DECchip 21064 Mode.
• 1 - DECchip 21064-A275 Mode.
3:0 Revision [ read-only ]
Indicates the revision level of the bus interface (C³ or C4) device.
• 10002 - rev C4 (This is the first revision to support 4-CPUs.)
• 10012 - rev C4-b.
• 10102 - rev C4-c. ( support for expansion I/O.)
Functions located elsewhere on the CPU module 129