Sable CPU Module Specification
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Sable CPU Module Specification

Sable CPU Module Specification Sable CPU Module Specification

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Copyright © 1993 Digital Equipment Corporation. 4.11.1 C4 Revision Register - CSR15 CSR offset = 1E0 16 Figure 56: C4 Revision Register (CRR) Disable CPU Node (RW) Forced Dcache Inv (RW) Enable I/O Retry (RW) Disable Duplicate Tag Parity Check (RW) Cache Interface Speed Bits (RW) CPU Mode (RO) Revision (RO) Disable CPU Node (RW) Forced Dcache Inv (RW) Enable I/O Retry (RW) Disable Duplicate Tag Parity Check (RW) Cache Interface Speed Bits (RW) CPU Mode (RO) Revision (RO) 6666555555555544 4444444433333333 3322222222221111 111111 3210987654321098 7654321098765432 1098765432109876 5432109876543210 Table 46: C4 Revision Register Description Field Description 63 Disable CPU Node [ read/write ] The state of this bit must match bit . 56 Forced Dcache Inv [ read/write ] The state of this bit must match bit . 49 Enable I/O Retry [ read/write ] The state of this bit must match bit . 47 Disable Duplicate Tag Parity Check [ read/write ] Cleared on power-up. When set, disables parity checking logic for the duplicate tag in the bus interface ASICs. When clear, duplicate tag parity checking may be enabled or disabled as programmed by CSR0 bit 34. This bit only controls the ODD slice ASIC. 46:40 Cache Interface Speed Bits [ read/write ] The state of these bits must match the bits in field . 36 CPU Mode [ read-only ] 128 Functions located elsewhere on the CPU module

Table 46 (Cont.): C4 Revision Register Description Field Description Copyright © 1993 Digital Equipment Corporation. 35:32 Revision [ read-only ] The state of these bits must match bits 31 Disable CPU Node [ read/write ] Cleared on power-up. When set, this bit disables a CPU from probing the backup cache and participating in system bus transactions. The state of this bit must match bit . 24 Forced Dcache Inv [ read/write ] Cleared on power-up. When set forces all CBUS writes to invalidate the processors d-cache regardless of whether it hits in the duplicate tag. This is a feature for diagnostics. The state of this bit must match bit 17 Enable I/O Retry [ read/write ] Cleared on power-up. When this bit is set, read and writes to I/O space will be re-tried if signaled by the I/O module. If clear, the retry signaling mechanism is treated as an error and logged in CSR-7 (CBE). The state of this bit must match bit 15 Disable Duplicate Tag Parity Check [ read/write ] Cleared on power-up. When set, disables parity checking logic for the duplicate tag in the interface ASICS. When clear, duplicate tag parity checking may be enabled or disabled as programmed by CSR0 bit 2. This bit only controls the EVEN slice asic. 14:8 Cache Interface Speed Bits [ read/write ] Cleared on power-up. When set, each bit corresponds to a control signal which can be slightly shifted in time, thereby allowing greater flexibility in operating speed combinations between processor and system bus. The state of this bit must match bit 4 CPU Mode [ read-only ] Indicates the pin bus mode for which the ASIC has autoconfigured. This is a read-only field. • 0 - DECchip 21064 Mode. • 1 - DECchip 21064-A275 Mode. 3:0 Revision [ read-only ] Indicates the revision level of the bus interface (C³ or C4) device. • 10002 - rev C4 (This is the first revision to support 4-CPUs.) • 10012 - rev C4-b. • 10102 - rev C4-c. ( support for expansion I/O.) Functions located elsewhere on the CPU module 129

Copyright © 1993 Digital Equipment Corporation.<br />

4.11.1 C4 Revision Register - CSR15<br />

CSR offset = 1E0 16<br />

Figure 56: C4 Revision Register (CRR)<br />

Disable <strong>CPU</strong> Node (RW)<br />

Forced Dcache Inv (RW)<br />

Enable I/O Retry (RW)<br />

Disable Duplicate Tag Parity Check (RW)<br />

Cache Interface Speed Bits (RW)<br />

<strong>CPU</strong> Mode (RO)<br />

Revision (RO)<br />

Disable <strong>CPU</strong> Node (RW)<br />

Forced Dcache Inv (RW)<br />

Enable I/O Retry (RW)<br />

Disable Duplicate Tag Parity Check (RW)<br />

Cache Interface Speed Bits (RW)<br />

<strong>CPU</strong> Mode (RO)<br />

Revision (RO)<br />

6666555555555544<br />

4444444433333333<br />

3322222222221111<br />

111111<br />

3210987654321098<br />

7654321098765432<br />

1098765432109876<br />

5432109876543210<br />

Table 46: C4 Revision Register Description<br />

Field Description<br />

63 Disable <strong>CPU</strong> Node [ read/write ]<br />

The state of this bit must match bit .<br />

56 Forced Dcache Inv [ read/write ]<br />

The state of this bit must match bit .<br />

49 Enable I/O Retry [ read/write ]<br />

The state of this bit must match bit .<br />

47 Disable Duplicate Tag Parity Check [ read/write ]<br />

Cleared on power-up. When set, disables parity checking logic for the duplicate tag in the<br />

bus interface ASICs. When clear, duplicate tag parity checking may be enabled or disabled as<br />

programmed by CSR0 bit 34. This bit only controls the ODD slice ASIC.<br />

46:40 Cache Interface Speed Bits [ read/write ]<br />

The state of these bits must match the bits in field .<br />

36 <strong>CPU</strong> Mode [ read-only ]<br />

128 Functions located elsewhere on the <strong>CPU</strong> module

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