Sable CPU Module Specification

4.11 Miss Address Register - CSR14
CSR offset = 1C0 16
Copyright © 1993 Digital Equipment Corporation.
The Miss Address Register captures the System-bus read or exchange address on
every miss with address bit not set, and holds the 64th sample until a sample
valid flag is cleared. The read or exchange may have resulted from a 21064 read or
write transaction. The latching strobe is skewed by 62 counts between the low and
high longwords of CSR14, or 2 counts from high to low longwords.
The counters used for sampling are free running and no reset of the counter occurs
when the MADR VALID flag in CSR7 is cleared. This means that the next sample
frozen after clearing this flag could occur between 1 and 64 transactions later.
Figure 55: Miss Address Register Low (MADRL)
6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9
ADDRESS (RO)
TRANSACTION TYPE (RO)
MADR VALID (RO)
TRANSACTION TYPE (RO)
MADR VALID (RO)
Table 45: Miss Address Register Low Description
Field Description
ADDRESS (RO)
8 7 6 5 4 3 2 1 0
63:34 ADDRESS [ read-only ]
Undefined on power-up. Address field , from CAD.
33 TRANSACTION TYPE [ read-only ]
Undefined on power-up. The commander transaction type, set indicates read cleared indicates
exchange.
32 MADR VALID [ read-only ]
Clear on power-up. When set this bit indicates that this sample is valid. This bit is a read-only
copy of csr7 bit 63.
31:2 ADDRESS [ read-only ]
Undefined on power-up. Address field , from CAD.
1 TRANSACTION TYPE [ read-only ]
Undefined on power-up. The commander transaction type, set indicates read cleared indicates
exchange.
0 MADR VALID [ read-only ]
Cleared on power-up. When set this bit indicates that this sample is valid. This bit is a read-only
copy of csr7 bit 31.
Functions located elsewhere on the CPU module 127