Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. Table 43 (Cont.): System Interrupt Clear Register Description Field Description 34 UNDEFINED [ read-only ] Undefined 33 SYSTEM EVENT CLEAR [ read/write ] Cleared on power-up. A read of this register returns the state of the request signal to the processor. A write to this register with a ‘‘1’’ in this bit position will clear the latched CSYS_ EVENT_L interrupt signal driven to the local CPU. This interrupt can be masked in the 21064 chip. 32 INTERVAL TIMER INTERRUPT CLEAR [ read/write ] Cleared on power-up. A read of this register returns the state of the interrupt signal to the processor. A write to this register with a ‘‘1’’ in this bit position will clear the latched CINT_TIM interrupt signal driven to the local CPU. This interrupt can be masked in the 21064 chip. 3 UNDEFINED [ read/write ] 2 System-bus ERROR INTERRUPT CLEAR [ read/write ] Cleared on power-up. A read of this register returns the state of the interrupt signal to the processor. A STQ to this register with a ‘‘1’’ in this bit position will clear the latched C_ERR_L interrupt signal driven to the local CPU. This interrupt can be masked in the 21064 chip. Interrupts generated by errors detected by this node may be disabled via bit in CSR6. 1 UNDEFINED [ read-only ] Undefined 0 UNDEFINED [ read-only ] Undefined 124 Functions located elsewhere on the CPU module
4.10 Address Lock Register - CSR13 CSR offset = 1A0 16 Copyright © 1993 Digital Equipment Corporation. The Address Lock Register is required by the Alpha Architecture Handbook to support the LDxL and STxC instructions. This is supported on Cobra in ‘‘memory like’’ regions only (Address is ‘‘0’’). This register will latch the address and set the Lock Address Valid bit when a LDxL instruction to memory address space is executed. The Lock Address Valid bit will be cleared when a STxC to any location or a Systembus write to the locked location occurs even if the write is from this node, or by explicitly clearing it by writing bit . If the Lock Address Valid bit is set, and a LDxL to a different location occurs, the contents of the Lock Address field will be updated with the new address. The resolution of the address lock in the system is a single aligned 32 byte block. NOTE The system software shall ensure that the state of the lock VALID flag in the low longword is consistent with the lock flag in the upper longword by performing quadword writes. The lock flag must always be cleared before returning from PALmode. Figure 54: Address Lock Register (ADLK) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 LOCK ADDRESS (RO) LOCK ADDRESS VALID (RW) LOCK ADDRESS (RO) LOCK ADDRESS VALID (RW) Table 44: Address Lock Register Description Field Description 8 7 6 5 4 3 2 1 0 63:35 LOCK ADDRESS [ read-only ] Set on power-up. A LDxL instruction to memory address space from this nodes processor will cause the contents of this register to be updated with the lock address. The contents are invalid when the LOCK ADDRESS VALID bit is clear. Bit 63 will always read as zero. 32 LOCK ADDRESS VALID [ read/write ] When set this bit indicates that the LOCK ADDRESS field is valid and a STxC will succeed. This bit is cleared on power-up, by a write from the System-bus to the locked location, by a STxC from the processor, or by writing a ‘‘1’’ to this bit. 31:3 LOCK ADDRESS [ read-only ] Functions located elsewhere on the CPU module 125
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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Page 89 and 90: Copyright © 1993 Digital Equipment
Page 99 and 100: CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
Page 103 and 104: Figure 41: B-Cache Control Register
Page 105 and 106: Table 28 (Cont.): B-Cache Control R
Page 107 and 108: Table 28 (Cont.): B-Cache Control R
Page 121 and 122: 4.3.1 Duplicate Tag Error Register
Page 123 and 124: 4.5 Lack of Cache Block Prefetch Co
Page 125 and 126: Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
Page 131 and 132: Table 38 (Cont.): System-bus Error
Page 133 and 134: 4.7.3 System-bus Error Address Low
Page 137 and 138: 4.8 Multiprocessor Configuration CS
Page 139: 4.9 System Interrupt Clear Register
Page 143 and 144: 4.11 Miss Address Register - CSR14
Page 145 and 146: Table 46 (Cont.): C4 Revision Regis
Page 147 and 148: Table 48 (Cont.): Interval Timer In
Page 149 and 150: Table 50: D-bus Microcontroller Clo
Page 151 and 152: Figure 58: Granting Order rule 4 CP
Page 155 and 156: Table 54 (Cont.): BIU_CTL Field Des
Page 157 and 158: Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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