Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 43 (Cont.): System Interrupt Clear Register Description
Field Description
34 UNDEFINED [ read-only ]
Undefined
33 SYSTEM EVENT CLEAR [ read/write ]
Cleared on power-up. A read of this register returns the state of the request signal to the
processor. A write to this register with a ‘‘1’’ in this bit position will clear the latched CSYS_
EVENT_L interrupt signal driven to the local CPU. This interrupt can be masked in the 21064
chip.
32 INTERVAL TIMER INTERRUPT CLEAR [ read/write ]
Cleared on power-up. A read of this register returns the state of the interrupt signal to the
processor. A write to this register with a ‘‘1’’ in this bit position will clear the latched CINT_TIM
interrupt signal driven to the local CPU. This interrupt can be masked in the 21064 chip.
3 UNDEFINED [ read/write ]
2 System-bus ERROR INTERRUPT CLEAR [ read/write ]
Cleared on power-up. A read of this register returns the state of the interrupt signal to the
processor. A STQ to this register with a ‘‘1’’ in this bit position will clear the latched C_ERR_L
interrupt signal driven to the local CPU. This interrupt can be masked in the 21064 chip. Interrupts
generated by errors detected by this node may be disabled via bit in CSR6.
1 UNDEFINED [ read-only ]
Undefined
0 UNDEFINED [ read-only ]
Undefined
124 Functions located elsewhere on the CPU module