Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
4.8.2 Interprocessor Interrupt Request Register - CSR11
CSR offset = 16016 Each CPU will have an Interprocessor Interrupt Request Register to support the
interprocessor interrupt IPR specified in the Alpha Architecture Handbook. As these
are System-bus visible, any System-bus commander including the owner can post
an interprocessor interrupt to any CPU. The interrupt is driven into the processor
signal identified internally as HIRR(3). In addition, a high IPL interrupt to each
local processor can be requested for halting a node by writing to the REQUEST_
NODE_HALT field in this register. Refer to the 21064 Processor Specification and
Chapter 7.
Figure 52: Interprocessor Interrupt Request Register (IPIR)
6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9
REQUEST NODE HALT INTERRUPT (RW)
UNDEFINED (RW)
REQUEST INT CPU (RW)
Table 42: Interprocessor Interrupt Request Register Description
Field Description
8 7 6 5 4 3 2 1 0
35 REQUEST NODE HALT INTERRUPT [ read/write ]
Cleared on power-up. Writing a "1" to this bit will cause a hardware interrupt similar to sys-event,
except for a single CPU only. Reading this register returns the state of the requested node halt
interrupt signal. Cleared by writing a "1" to the NODE HALT INT CLEAR bit in CSR12 (bit
).
32 UNDEFINED [ read/write ]
Undefined
0 REQUEST INT CPU [ read/write ]
Cleared on power-up. Writing a ‘‘1’’ will cause a hardware interrupt to be posted to the CPU
defined by the address of the CSR. Reading this register returns the state of the interrupt request
signal. Cleared by writing a ’0’.
122 Functions located elsewhere on the CPU module