Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. Table 40 (Cont.): System-bus Error Address High Register Description Field Description 27:24 SB1 [ read-only ] These bits should be ones. 23:21 COMMANDER ID [ read-only ] Undefined on power-up. Contains the commander identification code. The field is encoded as: 000 - CPU3 001 - CPU0 010 - CPU1 011 - CPU2 100 - I/O 0 (Standard I/O) 101 - I/O 1 (expansion I/O) 110 - RESERVED I/O 111 - RESERVED I/O 20:18 TRANSACTION TYPE [ read-only ] Undefined on power-up. The commander transaction request. The field is encoded as: 000 - READ 001 - RESERVED 010 - EXCHANGE 011 - RESERVED 100 - WRITE 101 - RESERVED 110 - RESERVED 111 - NUT 17:2 EXCHANGE ADDRESS [ read-only ] Undefined on power-up. Contains the tag, of the victimized cache location. Refer to the Cobra System Bus Specification for further details. 1:0 SBO [ read-only ] These bits should be ones. 120 Functions located elsewhere on the CPU module
4.8 Multiprocessor Configuration CSR Definitions 4.8.1 Processor Mailbox Register - CSR10 Copyright © 1993 Digital Equipment Corporation. CSR offset = 14016 The Processor Mailbox Register allows any System-bus commander to communicate with any other System-bus commander (implementing the Processor Mailbox Register) without the need for any memory subsystem. This is primarily intended to be used during the initialization of the system and system exception processing. Figure 51: Processor Mailbox Register (PMBX) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 XMIT/RCV (RW) Table 41: Processor Mailbox Register Description Field Description 8 7 6 5 4 3 2 1 0 63:0 XMIT/RCV [ read/write ] Cleared on power-up. The protocol used in communication between the two processors is completely under software control. Functions located elsewhere on the CPU module 121
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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Page 85 and 86: Copyright © 1993 Digital Equipment
Page 99 and 100: CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
Page 103 and 104: Figure 41: B-Cache Control Register
Page 105 and 106: Table 28 (Cont.): B-Cache Control R
Page 107 and 108: Table 28 (Cont.): B-Cache Control R
Page 121 and 122: 4.3.1 Duplicate Tag Error Register
Page 123 and 124: 4.5 Lack of Cache Block Prefetch Co
Page 125 and 126: Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
Page 131 and 132: Table 38 (Cont.): System-bus Error
Page 133 and 134: 4.7.3 System-bus Error Address Low
Page 135: Copyright © 1993 Digital Equipment
Page 139 and 140: 4.9 System Interrupt Clear Register
Page 141 and 142: 4.10 Address Lock Register - CSR13
Page 143 and 144: 4.11 Miss Address Register - CSR14
Page 145 and 146: Table 46 (Cont.): C4 Revision Regis
Page 147 and 148: Table 48 (Cont.): Interval Timer In
Page 149 and 150: Table 50: D-bus Microcontroller Clo
Page 151 and 152: Figure 58: Granting Order rule 4 CP
Page 155 and 156: Table 54 (Cont.): BIU_CTL Field Des
Page 157 and 158: Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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