Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. 4.7.4 System-bus Error Address High Register - CSR9 CSR offset = 120 16 The System-bus Error Address High Register is updated by this nodes commander transactions or by System-bus errors and contains the actual data found on the System-bus during the latest C/A cycle. Whenever a System-bus error is detected and logged in the CBE register, the contents of this register are frozen until all of the errors, not missed error, indications in the CBE Register are cleared. For System-bus command/address cycles that are not acknowledged, the failing address is latched only in the error logging bits . Bits do not contain valid information when this type of error is logged. Figure 50: System-bus Error Address High Register (CBEAH) ODD WRITE MASKS (RO) SB1 (RO) COMMANDER ID (RO) TRANSACTION TYPE (RO) EXCHANGE ADDRESS (RO) SBO (RO) EVEN WRITE MASKS (RO) SB1 (RO) COMMANDER ID (RO) TRANSACTION TYPE (RO) EXCHANGE ADDRESS (RO) SBO (RO) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Table 40: System-bus Error Address High Register Description Field Description 63:60 ODD WRITE MASKS [ read-only ] 118 Functions located elsewhere on the CPU module
Copyright © 1993 Digital Equipment Corporation. Table 40 (Cont.): System-bus Error Address High Register Description Field Description Odd Write Masks: (RO) This field contains the odd longword write MASKS bits used in the EV transaction that caused this CBUS cycle. Specifically: • CBEAH = EV Write Mask bit 7 • CBEAH = EV Write Mask bit 5 • CBEAH = EV Write Mask bit 3 • CBEAH = EV Write Mask bit 1 NOTE: The CPU uses the MASKS bits to communicate different data during READ cycles, and this data is related over these CBUS signals as well. 59:56 SB1 [ read-only ] Undefined on power-up. These bits should be ones. 55:53 COMMANDER ID [ read-only ] Undefined on power-up. Contains the commander identification code. The field is encoded as: CID Module 000 - CPU3 001 - CPU0 010 - CPU1 011 - CPU2 100 - I/O 0 (Standard I/O) 101 - I/O 1 (expansion I/O) 110 - RESERVED I/O 111 - RESERVED I/O 52:50 TRANSACTION TYPE [ read-only ] Undefined on power-up. The commander transaction request. The field is encoded as: 000 - READ 001 - RESERVED 010 - EXCHANGE 011 - RESERVED 100 - WRITE 101 - RESERVED 110 - RESERVED 111 - NUT 49:34 EXCHANGE ADDRESS [ read-only ] Undefined on power-up. Contains the tag, of the victimized cache location. Refer to the Cobra System Bus Specification for further details. 33:32 SBO [ read-only ] These bits should be ones. 31:28 EVEN WRITE MASKS [ read-only ] Even Write Masks: (RO) This field contains the even longword write MASKS bits used in the EV transaction that caused this CBUS cycle. Specifically: • CBEAH = EV Write Mask bit 6 • CBEAH = EV Write Mask bit 4 • CBEAH = EV Write Mask bit 2 • CBEAH = EV Write Mask bit 0 Functions located elsewhere on the CPU module 119
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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Page 83 and 84: Copyright © 1993 Digital Equipment
Page 99 and 100: CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
Page 103 and 104: Figure 41: B-Cache Control Register
Page 105 and 106: Table 28 (Cont.): B-Cache Control R
Page 107 and 108: Table 28 (Cont.): B-Cache Control R
Page 121 and 122: 4.3.1 Duplicate Tag Error Register
Page 123 and 124: 4.5 Lack of Cache Block Prefetch Co
Page 125 and 126: Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
Page 131 and 132: Table 38 (Cont.): System-bus Error
Page 133: 4.7.3 System-bus Error Address Low
Page 137 and 138: 4.8 Multiprocessor Configuration CS
Page 139 and 140: 4.9 System Interrupt Clear Register
Page 141 and 142: 4.10 Address Lock Register - CSR13
Page 143 and 144: 4.11 Miss Address Register - CSR14
Page 145 and 146: Table 46 (Cont.): C4 Revision Regis
Page 147 and 148: Table 48 (Cont.): Interval Timer In
Page 149 and 150: Table 50: D-bus Microcontroller Clo
Page 151 and 152: Figure 58: Granting Order rule 4 CP
Page 155 and 156: Table 54 (Cont.): BIU_CTL Field Des
Page 157 and 158: Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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