Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 38 (Cont.): System-bus Error Register Description
Field Description
6 PAR ERR ON READ DATA - REQ [ read/write ]
Cleared on power-up. Set when a parity error was detected on returned read data longwords 2
or 0 as a commander. Write ‘‘1’’ to clear.
5 MISSED ERR ON WRITE DATA - RESP [ read/write ]
Cleared on power-up. Set when a parity error was detected on longwords 2 or 0 as a responder
or bystander or a write data cycle from this commander was not ack’ed and the error command
and address could not be saved in the CBEAL register. Write ‘‘1’’ to clear.
4 PAR ERR ON WRITE DATA - RESP [ read/write ]
Cleared on power-up. Set when a parity error was detected on even longwords 2 or 0 as a
responder or a bystander in the case of accepting write data to update the B-Cache. Write ‘‘1’’
to clear. Only detects parity error on longwords 2 and 0.
3 MISSED C/A ERR [ read/write ]
Cleared on power-up. Set when a parity error was detected on the even C/A longwords (2,0) or
the C/A cycle was not ack’ed from this commander and the error command and address could
not be saved in the CBEAL register. Write ‘‘1’’ to clear.
2 C/A PAR ERR [ read/write ]
Cleared on power-up. Set when a parity error was detected on the even C/A longwords (2,0)
regardless of the address or which node was the commander. A CPU node checks its own parity
as a commander. Write ‘‘1’’ to clear.
1 RESERVED DIAGNOSTIC [ read/write ]
Cleared on power-up. Set as a result of an error event being communicated between the even
and odd interface chips. This bit is for chip debug and should not be used by system software.
The address is not held in CSR 8 and 9 when this bit is set. Write ‘‘1’’ to clear.
116 Functions located elsewhere on the CPU module