Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 38 (Cont.): System-bus Error Register Description
Field Description
Cleared on power-up. This bit is valid if a parity error is detected by this module, reading a ‘‘1’’
indicates an error on command/address longword 1 System-bus bits , during the C/A
cycle portion of a System-bus transaction. C/A PAR ERR LW1 ERR will remain valid until the
Data ERR bits (34) is cleared.
39 MISSED PAR ERR ON READ DATA - REQ H [ read/write ]
Cleared on power-up. Set when a parity error was detected on returned read data longwords 3
or 1 as a commander and the error command and address could not be saved in the CBEAH
register. Write 1 to clear.
38 PAR ERR ON READ DATA - REQ H [ read/write ]
Cleared on power-up. Set when a parity error was detected on returned read data longwords 3
or 1 as a commander. Write ‘‘1’’ to clear.
37 MISSED PAR ERR ON WRITE DATA - RESP H [ read/write ]
Cleared on power-up. Set when a parity error was detected on longwords 3 or 1 as a responder
or bystander the error command and address could not be saved in the CBEAH register. Write
‘‘1’’ to clear.
36 PAR ERR ON WRITE DATA - RESP H [ read/write ]
Cleared on power-up. Set when a parity error was detected on odd longwords 3 or 1 as a
responder or a bystander in the case of accepting write data to update the B-Cache. Write ‘‘1’’
to clear. Only detects parity error on longwords 3 and 1.
35 MISSED C/A PAR ERR [ read/write ]
Cleared on power-up. Set when a parity error was detected on the even C/A longwords (3,1) and
the error command and address could not be saved in the CBEAH register. Write ‘‘1’’ to clear.
34 C/A PAR ERR [ read/write ]
Cleared on power-up. Set when a parity error was detected on the even C/A longwords (3,1)
regardless of the address or which node was the commander. A CPU node checks its own parity
as a commander. Write ‘‘1’’ to clear.
33 RESERVED DIAGNOSTIC H [ read/write ]
Cleared on power-up. Set as a result of an error event being communicated between the even
and odd interface chips. This bit is for chip debug and should not be used by system software.
The address is not held in CSR 8 and 9 when this bit is set. Write ‘‘1’’ to clear.
31 MADR VALID [ read/write ]
Cleared on power-up. This bit will be set when the miss counter overflows and holds sampled
miss address into the MADRL register. The miss address is sampled every 64th B-Cache miss
by a free running miss transaction counter. When this bit is set MADRL have valid miss
contents. This bit being set inhibits capturing a new sample, but does not inhibit the counter from
incrementing. A copy of this bit is readable from bit 0 of the MADRL register. Write ‘‘1’’ to clear.
30:25 MISS COUNT [ read-only ]
Set to 111110 on power-up. The six bit miss address counter is readable in this field.
16 RETRY FAILED [ read/write 1 to clear ]
RETRY FAILED: (RW) Cleared on Power-up. Reading a "1" indicates that a CBUS retry was
seen when not expected. This indicates that a CBUS retry signal was seen on the CBUS, but
RETRY is not enabled in CSR15. When this occurs, the CPU command that was retried will
acknowledge to EV with a CACK of HARD_ERR, and this bit will be set. The setting of this bit
will NOT cause a CBUS C_ERRL or CPU interrupt to occur other than the HARD_ERR machine
check to the CPU that failed.
114 Functions located elsewhere on the CPU module