Sable CPU Module Specification

Table 38: System-bus Error Register Description
Field Description
Copyright © 1993 Digital Equipment Corporation.
63 MADR VALID [ read/write ]
Cleared on power-up. Has same function as bit 31, but indicates another valid sample in MADRL
that occurs 62 miss counts offset from the sample in the other half of these registers.
Effectively providing two samples every 64 misses. A copy of this bit is readable from bit 0 of
the MADRL register. Write ‘‘1’’ to clear.
62:57 MISS COUNT H [ read-only ]
Set to 000000 on power-up. The six bit miss address counter is readable in this field.
48 RETRY FAILED [ read/write 1 to clear ]
RETRY FAILED: (RW) Cleared on Power-up. Reading a "1" indicates that a CBUS retry was
seen when not expected. This indicates that a CBUS retry signal was seen on the CBUS, but
RETRY is not enabled in CSR15. When this occurs, the CPU command that was retried will
acknowledge to EV with a CACK of HARD_ERR, and this bit will be set. The setting of this bit
will NOT cause a CBUS C_ERRL or CPU interrupt to occur other than the HARD_ERR machine
check to the CPU that failed.
47:46 UNDEFINED H [ read/write 1 to clear ]
Cleared on power-up. Undefined usage.
45 DATA PAR ERR LW7 ERR [ read-only ]
Cleared on power-up. This bit is valid if a parity error is detected by this module, reading a ‘‘1’’
indicates an error on data longword 7 System-bus bits , during the second data cycle
portion of a System-bus transaction. DATA PAR ERR LW7 ERR will remain valid until the Data
ERR bits (38,36) are cleared.
44 DATA PAR ERR LW5 ERR [ read-only ]
Cleared on power-up. This bit is valid if a parity error is detected by this module, reading a ‘‘1’’
indicates an error on data longword 5 System-bus bits , during the second data cycle
portion of a System-bus transaction. DATA PAR ERR LW5 ERR will remain valid until the Data
ERR bits ( and ) are cleared.
43 DATA PAR ERR LW3 ERR [ read-only ]
Cleared on power-up. This bit is valid if a parity error is detected by this module, reading a
‘‘1’’ indicates an error on data longword 3 System-bus bits , during the first data cycle
portion of a System-bus transaction. DATA PAR ERR LW3 ERR will remain valid until the Data
ERR bits (38,36) are cleared.
42 DATA PAR ERR LW1 ERR [ read-only ]
Cleared on power-up. This bit is valid if a parity error is detected by this module, reading a ‘‘1’’
indicates an error on data longword 1 System-bus bits , during the first data cycle portion
of a System-bus transaction. DATA PAR ERR LW1 ERR will remain valid until the Data ERR bits
(38,36) are cleared.
41 C/A PAR ERR LW3 ERR [ read-only ]
Cleared on power-up. This bit is valid if a parity error is detected by this module, reading a ‘‘1’’
indicates an error on command/address longword 3 System-bus bits , during the C/A
cycle portion of a System-bus transaction. C/A PAR ERR LW3 ERR will remain valid until the
Data ERR bits (34) is cleared.
40 C/A PAR ERR LW1 ERR [ read-only ]
Functions located elsewhere on the CPU module 113