Sable CPU Module Specification
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Sable CPU Module Specification

Sable CPU Module Specification Sable CPU Module Specification

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Copyright © 1993 Digital Equipment Corporation. Table 37 (Cont.): System-bus Control Register Description Field Description 11 ENB C-bus ERROR INTERRUPT [ read/write ] Cleared on power-up to disable the System-bus C_ERR_L interrupt signal from being driven due to errors encountered by this node. This bit does not disable reception of this interrupt signal. 7:5 COMMANDER ID [ read-only ] Identifies the CPU as being CPU0, CPU1, CPU2, or CPU3 based on the System-bus commander ID. Writes have no effect. Regardless of being CPU0 or CPU1 performing a read of this CSR, the contents of this field are returned with the CPU ID of the CPU commanding the CSR read. 011 CPU2 010 CPU1 001 CPU0 000 CPU3 4 FORCE SHARED [ read/write ] Cleared on power-up. When set asserts CSHARED_L on all System-bus transactions. 3 ENABLE PAR CHK [ read/write ] Cleared on power-up. When set, longword parity checking on the System-bus for both the C/A and data portion of cycle (if responder) is enabled for C/A longwords 1 and 0 and data longwords 2 and 0. 2:1 C/A WRONG PAR [ read/write ] Cleared on power-up. When set forces wrong parity on Longwords 2 and 0 respectively during the C/A portion of the next C/A cycle from this node to the System-bus. Once this cycle has occurred the C/A WRONG PAR bits are automatically cleared. 0 DATA WRONG PAR [ read/write ] Cleared on power-up. When set forces wrong parity on longwords 6,4,2 and 0 during both data portions of the next System-bus cycle to which this node responds. Once this cycle has occurred the DATA WRONG PAR bit is automatically cleared. This should not be set when any of the C/A WRONG PAR bits are set as a responder is not able to log both wrong C/A parity and wrong data parity in the same System-bus transaction. 110 Functions located elsewhere on the CPU module

4.7.2 System-bus Error Register - CSR7 Copyright © 1993 Digital Equipment Corporation. CSR offset = E016 The System-bus Error Register is updated every System-bus cycle. Whenever a System-bus error is detected, the contents of this register are frozen until the ER- ROR bits are cleared. The contents of the register are not updated while the error flags are set, the lost error flags do not inhibit error logging. NOTE Even though the CBE register will be updated with the latest cycle on the System-bus, the contents of this register in the non-error case will always be the cycle that was issued to actually read the CBE register. This is because the register is accessed via a System-bus cycle. If a tag control or tag store parity error is detected then the C/A NOT ACKED and/or the WRITE DATA NOT ACKED bits are set. Functions located elsewhere on the CPU module 111

4.7.2 System-bus Error Register - CSR7<br />

Copyright © 1993 Digital Equipment Corporation.<br />

CSR offset = E016 The System-bus Error Register is updated every System-bus cycle. Whenever a<br />

System-bus error is detected, the contents of this register are frozen until the ER-<br />

ROR bits are cleared. The contents of the register are not updated while the error<br />

flags are set, the lost error flags do not inhibit error logging.<br />

NOTE<br />

Even though the CBE register will be updated with the latest cycle on the<br />

System-bus, the contents of this register in the non-error case will always be<br />

the cycle that was issued to actually read the CBE register. This is because<br />

the register is accessed via a System-bus cycle.<br />

If a tag control or tag store parity error is detected then the C/A NOT ACKED<br />

and/or the WRITE DATA NOT ACKED bits are set.<br />

Functions located elsewhere on the <strong>CPU</strong> module 111

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