Sable CPU Module Specification

Table 37: System-bus Control Register Description
Field Description
Copyright © 1993 Digital Equipment Corporation.
46 SELECT DRACK H [ read/write ]
Cleared on power-up. This bit is reserved for timing configuration selection of the 21064 response
strobe DRACK. When set the DRACK strobe timing is shifted by six nanoseconds. The
state of this bit must match bit in this register.
45 2nd QW SELECT H [ read/write ]
Cleared on power-up. This bit is reserved for timing configuration selection of the second quadword
of returned data to the 21064. When set the data mux control strobe is shifted by six
nanoseconds. The state of this bit must match bit in this register.
43 ENB C-bus ERROR INTERRUPT H [ read/write ]
Cleared on power-up. The state of this bit must match bit in this register.
39:37 COMMANDER ID [ read-only ]
Identifies the CPU as being CPU0, CPU1, CPU2, or CPU3 based on the System-bus commander
ID. Writes have no effect. Regardless of being CPU0 or CPU1 performing a read of this CSR,
the contents of this field are returned with the CPU ID of the CPU commanding the CSR read.
011 CPU2
010 CPU1
001 CPU0
000 CPU3
36 FORCE SHARED H [ read/write ]
Cleared on power-up. When set asserts CSHARED_L on all System-bus transactions.
35 ENB PARITY CHK H [ read/write ]
Cleared on power-up. When set, longword parity checking on the System-bus for both the C/A
and data portion of cycle (if responder) is enabled for C/A longwords 3 and 2 and data longwords
7,5,3 and 1.
34:33 C/A WRONG PAR H [ read/write ]
Cleared on power-up. When set forces wrong parity on Longwords 3 and 1 respectively during
the C/A portion of the next C/A cycle from this node to the System-bus. Once this cycle has
occurred the C/A WRONG PAR bits are automatically cleared.
32 DATA WRONG PAR H [ read/write ]
Cleared on power-up. When set forces wrong parity on longwords 7,5,3 and 1 during both data
portions of the next System-bus cycle to which this node responds. Once this cycle has occurred
the DATA WRONG PAR bit is automatically cleared. This should not be set when any of the C/A
WRONG PAR bits are set as a responder is not able to log both wrong C/A parity and wrong
data parity in the same System-bus transaction.
14 SELECT DRACK [ read/write ]
Cleared on power-up. This bit is reserved for timing configuration selection of the 21064 response
strobe DRACK. When set the DRACK strobe timing is shifted by six nanoseconds.
13 2nd QW SELECT [ read/write ]
Cleared on power-up. This bit is reserved for timing configuration selection of the second quadword
of returned data to the 21064. When set the data mux control strobe is shifted by six
nanoseconds.
12 DISABLE BACK-TO-BACK ARBITRATION [ read/write ]
FOR DIAGNOSTICS ONLY. Cleared on power-up. This bit is reserved for diagnostic testing,
when set the behavior of the C-bus arbiter is modified. This bit is used by CPU0 only.
Functions located elsewhere on the CPU module 109