Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 35 (Cont.): Duplicate Tag Error Register Description
Field Description
Undefined on power-up. Contains the last P-Cache duplicate tag. If a parity error occurs in the
P-Cache duplicate tag store, then the contents of this register will be frozen until the ERROR bits
have been cleared. This field is only updated when memory space references occur while the
register is not frozen.
60:52 DUPTAG BANK1 TAG [ read-only ]
51 DUPTAG BANK0 PARITY [ read-only ]
50:42 DUPTAG BANK0 TAG [ read-only ]
41:34 DUPTAG STORE OFFSET [ read-only ]
Undefined on power-up. Contains the last Duplicate Tag Store Offset. If a parity error occurs in
the duplicate tag store, then the DUP TAG STORE OFFSET will remain for that cycle until the
ERROR bits have been cleared.
This field is only updated when memory space references occur while the register is not frozen.
33 ERROR [ read/write 1 to clear ]
Cleared on power-up. Set when, a Primary D-Cache duplicate tag store parity error has been
detected to hold the contents of this register until this flag is cleared.
32 MISSED ERROR OCCURRED [ read/write 1 to clear ]
This bit is set when a Primary D-Cache duplicate tag store parity error bit was set and another
parity error is detected. When set, logging in this CSR is inhibited and further interrupts from this
error are suppressed. This bit is cleared on power-up.
29 DUPTAG BANK1 PARITY [ read-only ]
28:20 DUPTAG BANK1 TAG [ read-only ]
19 DUPTAG BANK0 PARITY [ read-only ]
18:10 DUPTAG BANK0 TAG [ read-only ]
9:2 DUPTAG STORE OFFSET [ read-only ]
Undefined on power-up. Contains the last Duplicate Tag Store Offset. If a parity error occurs in
the duplicate tag store, then the DUP TAG STORE OFFSET will remain for that cycle until the
ERROR bits have been cleared.
This field is only updated when memory space references occur while the register is not frozen.
1 ERROR [ read/write 1 to clear ]
This bit is set when a PRIMARY D-CACHE DUPLICATE TAG STORE PARITY ERROR is detected. The contents of
this register are held until this error flag is cleared. Cleared on power-up.
0 MISSED ERROR OCCURRED [ read/write 1 to clear ]
Cleared on power-up. Set when, a Primary D-Cache duplicate tag store parity error bit was set
and another one is detected. When set, logging in this CSR is inhibited and further interrupts
from this error are suppressed.
4.4 Lack of Duplicate Primary Instruction Cache Tag Store
Because the primary instruction cache is a virtual cache, all cache coherence is managed
by the system software. Thus no hardware invalidates of the instruction cache
will be performed. Also because very little writing to shared I-stream locations occur,
the benefit of ‘‘selective’’ updating is diminished. As such there is no duplicate
primary instruction cache tag store on the Cobra CPU module.
106 Functions located elsewhere on the CPU module