Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

70 B-Cache Control Register (BCC-CSR0, offset = 0000) ................ 214 71 B-Cache Correctable Error (BCCE-CSR1, offset = 0020) .............. 215 72 B-Cache Correctable Error Address (BCCEA-CSR2, offset = 0040) ...... 215 73 B-Cache Uncorrectable Error (BCUE-CSR3, offset = 0060) . . .......... 216 74 B-Cache Uncorrectable Error Address (BCUEA-CSR4, offset = 0080) . . . . 216 75 Duplicate Tag Error Register (DTER-CSR5, offset = 00A0) . . .......... 217 76 Cobra-bus Control Register (CBCTL-CSR6, offset = 00C0) . . .......... 218 77 Cobra-bus Error Register (CBE-CSR7, offset = 00E0) ................ 219 78 Cobra-bus Error Address Low (CBEAL-CSR8, offset = 0100) .......... 220 79 Cobra-bus Error Address High (CBEAH-CSR9, offset = 0120) ......... 220 80 Processor Mailbox (PMBX-CSR10, offset = 0140) . .................. 220 81 Interprocessor Interrupt Request (IPIR-CSR11, offset = 0160) ......... 221 82 System Interrupt Clear Register (SIC-CSR12, offset = 0180) .......... 221 83 Address Lock Register (ADLK-CSR13, offset = 01A0) ................ 221 84 Miss Address Register Low (MADRL-CSR14, offset = 01C0) . .......... 222 85 C4 Revision Register (CRR-CSR15, offset = 01E0) .................. 222 TABLES 1 CPU Modules Variations . . . ................................... 7 2 Latencies for Single and Double Precision Divide Instructions ......... 10 3 Performance Counter 0 Input Selection . .......................... 15 4 Performance Counter 1 Input Selection . .......................... 16 5 ICCSR . ................................................... 19 6 BHE,BPE Branch Prediction Selection . .......................... 20 7 SL_CLR ................................................... 23 8 EXC_SUM ................................................. 27 9 HIRR . . ................................................... 29 10 MM_CSR .................................................. 41 11 Abox Control Register ........................................ 45 12 ALT Mode ................................................. 46 13 BIU Control Register Description ............................... 47 14 DECchip 21064-A275 BIU Control Register Description .............. 50 15 BC_SIZE .................................................. 53 16 BC_PA_DIS ................................................ 53 17 BIU_CTL Initialization Values ................................. 53 18 Producer-Consumer Classes ................................... 64 19 Opcode Summary (with Instruction Issue Bus) . . . .................. 69 20 Required PALcode Instructions ................................. 70 21 Instructions Specific to the 21064 ............................... 70 22 DECchip 21064 Cache Status Register . .......................... 71 23 DECchip 21064-A275 Cache Status Register ....................... 72 24 BIUSTAT ................................................. 75 25 Syndromes for Single-Bit Errors ................................ 78 26 ......................................................... 84 xii
27 Base Addresses for CSRs . . . ................................... 85 28 B-Cache Control Register Description . . .......................... 88 29 B-Cache Correctable Error Register Description . . .................. 92 30 B-Cache Correctable Error Address Register Description . . . .......... 95 31 B-Cache Uncorrectable Error Register Description .................. 98 32 B-Cache Uncorrectable Error Address Register Description . .......... 100 33 The 21064 B-Cache cycle times ................................. 102 34 System-bus B-Cache Access Time ............................... 102 35 Duplicate Tag Error Register Description ......................... 105 36 Data Integrity Reference . . ................................... 107 37 System-bus Control Register Description ......................... 109 38 System-bus Error Register Description . .......................... 113 39 System-bus Error Address Low Register Description ................ 117 40 System-bus Error Address High Register Description ................ 118 41 Processor Mailbox Register Description . .......................... 121 42 Interprocessor Interrupt Request Register Description ............... 122 43 System Interrupt Clear Register Description ...................... 123 44 Address Lock Register Description .............................. 125 45 Miss Address Register Low Description .......................... 127 46 C4 Revision Register Description ............................... 128 47 CSR Space ................................................. 130 48 Interval Timer Interrupt Generation . . . .......................... 130 49 D-bus Micro Port Mapping . ................................... 132 50 D-bus Microcontroller Clock Frequency . .......................... 133 51 D-bus Microcontroller System Control Bus Address ................. 133 52 Sable Arbitration Latency . . ................................... 136 53 CPU I²C Bus EEPROM Field Definitions ......................... 137 54 BIU_CTL Field Description . ................................... 138 56 BIU_CTL Initialization Values ................................. 140 57 CPU EEPROM Defaults . . . ................................... 141 58 ......................................................... 141 59 Cycle Request . . . ........................................... 144 60 Cycle Acknowledgment Types .................................. 145 61 Read Data Acknowledgment Types .............................. 145 62 Processor Initiated Transactions ............................... 146 63 System-bus Initiated Transactions .............................. 157 64 Processor Initiated Transactions - Control Flow . . .................. 158 65 System-bus Initiated Transactions - Control Flow . .................. 162 66 Invalidate Management - C-bus Caused .......................... 165 67 General Exception Isolation Matrix .............................. 167 68 Machine Check Isolation Matrix ................................ 168 69 Exception Priority/PAL Offset/SCB Offset/IPL . . . .................. 169 70 Hardware Interrupt Configuration .............................. 173 71 Interrupt Priority/SCB Offset/IPL ............................... 174 72 Tag/Tag Control Error Severity Matrix . .......................... 179 xiii
Page 1 and 2: Sable CPU Module Specification This
Page 3 and 4: CONTENTS Preface ..................
Page 5 and 6: 3.9.6 Data Cache Address Register (
Page 7 and 8: 7.1.1 Exception Handling ..........
Page 9 and 10: 11.4 Environmental Specifications -
Page 11: 25 MM_CSR .........................
Page 15 and 16: Preface Scope and Organization of t
Page 17 and 18: Copyright © 1993 Digital Equipment
Page 19 and 20: CHAPTER 1 CPU MODULE COMPONENTS AND
Page 23 and 24: 1.2 The Alpha AXP Architecture Copy
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Copyright © 1993 Digital Equipment
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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