Sable CPU Module Specification
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Sable CPU Module Specification

Sable CPU Module Specification Sable CPU Module Specification

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Copyright © 1993 Digital Equipment Corporation. 4.1.4.6 B-Cache Uncorrectable Error Address Register - CSR4 CSR offset = 8016 When a B-Cache tag store or control store parity error, or an uncorrectable EDC error has been detected, the B-Cache Uncorrectable Error Address Register contains the index of the B-Cache location that contains the error. The B-Cache Uncorrectable Error Address Register for CPU 0 is located at address 2.0000.0080 (hex), and for CPU 1 at address 2.0800.0080 (hex). Figure 45: B-Cache Uncorrectable Error Address Register (BCUEA) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 TAG VALUE H (RO) TAG PARITY H (RO) PREDICTED TAG PAR H (RO) B-CACHE MAP OFFSET H (RO) TAG VALUE (RO) TAG PARITY (RO) PREDICTED TAG PAR (RO) B-CACHE MAP OFFSET (RO) Table 32: B-Cache Uncorrectable Error Address Register Description Field Description 62:51 TAG VALUE H [ read-only ] Cleared on power-up. Contains the value of the Tag for the last B-Cache location accessed by the B-Cache controller. This register is updated when the BCUE UNCORRECTABLE and PARITY ERROR bits are clear. If LW 3 or LW 1 has an uncorrectable EDC error this field provides an address pointer into the B-Cache. 50 TAG PARITY H [ read-only ] Cleared on power-up. Contains the value of Tag Store Parity for the last B-Cache location accessed by the B-Cache controller. This register is updated when the BCUE UNCORRECTABLE and PARITY ERROR bits are clear. 49 PREDICTED TAG PAR H [ read-only ] 100 Functions located elsewhere on the CPU module

Copyright © 1993 Digital Equipment Corporation. Table 32 (Cont.): B-Cache Uncorrectable Error Address Register Description Field Description Cleared on power-up. Contains the value of the last System-bus predicted tag parity. The value of this bit will be frozen if a a parity error occurs in the tag, control store, or an EDC error is detected, on a victim write, a masked write to a shared location, a LDxL or STxC, victimization of a cache location, or a System-bus READ, WRITE or EXCHANGE. This register is updated when the BCUE UNCORRECTABLE and PARITY ERROR bits are clear. This has been added to provide to power-up diagnostics visibility to an internal parity tree. The value of this location is valid if the register is frozen and the cycle causing the error was a Systembus read or write or if the register is not frozen and the register is read (the EVEN parity of the address bits during the CSR read access will be found in this location.) This bit should be disregarded during normal system operation. Refer to Chapter 10 for further details. 48:32 B-CACHE MAP OFFSET H [ read-only ] Cleared on power-up. Contains the last B-Cache MAP index (address bits for 1MB backup cache, address bits 21:5 for 4MB backup cache) If a parity error occurs in the tag, or control bits, or and EDC error has been detected, then the contents of this register are frozen until the BCUE UNCORRECTABLE and PARITY ERROR bits are clear. If LW 3 or LW 1 has an uncorrectable EDC error this field provides an address pointer into the B-Cache. 30:19 TAG VALUE [ read-only ] Cleared on power-up. Contains the value of the Tag for the last B-Cache location accessed by the B-Cache controller. This register is updated when the BCUE UNCORRECTABLE and PARITY ERROR bits are clear. If LW 2 or LW 0 has an uncorrectable EDC error this field provides an address pointer into the B-Cache. 18 TAG PARITY [ read-only ] Cleared on power-up. Contains the value of Tag Store Parity for the last B-Cache location accessed by the B-Cache controller. This register is updated when the BCUE UNCORRECTABLE and PARITY ERROR bits are clear. 17 PREDICTED TAG PAR [ read-only ] Cleared on power-up. Contains the value of the last System-bus predicted tag parity. The value of this bit will be frozen if a parity error is detected in the tag, tag control store, or an EDC error is detected, when a System-bus System-bus READ, WRITE or EXCHANGE probe occurs. This register is updated when the BCUE UNCORRECTABLE and PARITY ERROR bits are clear. This has been added to provide to power-up diagnostics visibility to an internal parity tree. The value of this location is valid if the register is frozen and the cycle causing the error was a Systembus read or write (the EVEN parity of the address bits for 1MB cache) This bit should be disregarded during normal system operation. Refer to Chapter 10 for further details. 16:0 B-CACHE MAP OFFSET [ read-only ] Cleared on power-up. Contains the last B-Cache MAP index. If a parity error occurs in the tag, or control bits, or and EDC error has been detected, then the contents of this register are frozen until the BCUE UNCORRECTABLE and PARITY ERROR bits are clear. If LW 2 or LW 0 has an uncorrectable EDC error this field provides an address pointer into the B-Cache. 4.1.5 Back-up Cache Cycle Time Functions located elsewhere on the CPU module 101

Copyright © 1993 Digital Equipment Corporation.<br />

4.1.4.6 B-Cache Uncorrectable Error Address Register - CSR4<br />

CSR offset = 8016 When a B-Cache tag store or control store parity error, or an uncorrectable EDC<br />

error has been detected, the B-Cache Uncorrectable Error Address Register contains<br />

the index of the B-Cache location that contains the error.<br />

The B-Cache Uncorrectable Error Address Register for <strong>CPU</strong> 0 is located at address<br />

2.0000.0080 (hex), and for <strong>CPU</strong> 1 at address 2.0800.0080 (hex).<br />

Figure 45: B-Cache Uncorrectable Error Address Register (BCUEA)<br />

6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1<br />

3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0<br />

TAG VALUE H (RO)<br />

TAG PARITY H (RO)<br />

PREDICTED TAG PAR H (RO)<br />

B-CACHE MAP OFFSET H (RO)<br />

TAG VALUE (RO)<br />

TAG PARITY (RO)<br />

PREDICTED TAG PAR (RO)<br />

B-CACHE MAP OFFSET (RO)<br />

Table 32: B-Cache Uncorrectable Error Address Register Description<br />

Field Description<br />

62:51 TAG VALUE H [ read-only ]<br />

Cleared on power-up. Contains the value of the Tag for the last B-Cache location accessed by the<br />

B-Cache controller. This register is updated when the BCUE UNCORRECTABLE and PARITY<br />

ERROR bits are clear. If LW 3 or LW 1 has an uncorrectable EDC error this field provides an<br />

address pointer into the B-Cache.<br />

50 TAG PARITY H [ read-only ]<br />

Cleared on power-up. Contains the value of Tag Store Parity for the last B-Cache location<br />

accessed by the B-Cache controller. This register is updated when the BCUE UNCORRECTABLE<br />

and PARITY ERROR bits are clear.<br />

49 PREDICTED TAG PAR H [ read-only ]<br />

100 Functions located elsewhere on the <strong>CPU</strong> module

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