Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
4.1.4.5 B-Cache Uncorrectable Error Register - CSR3
CSR offset = 6016 The B-Cache Uncorrectable Error Register latches the state of the B-Cache tag and
control stores when a parity error or an EDC uncorrectable error (during the data
portion of the cycle) is detected. The contents of B-Cache Uncorrectable Error Address
Register are not updated while error flags are set, the lost error flag does not inhibit
error logging.
These errors are only detected by the B-Cache controller as a result of a processor
masked write hit to a shared location, a LDxL or STxC, victimization of a cache
location, or a System-bus READ, WRITE, or EXCHANGE transaction. (EDC errors
are not detected by the Cobra Bus interface ASICs on LDxL, and System-bus WRITE
transactions as a bystander or responder.)
Figure 44: B-Cache Uncorrectable Error Register (BCUE)
6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
EDC SYNDROME 3 (RO)
EDC SYNDROME 1 (RO)
BC EDC ERROR (RO)
UNCORRECTABLE ERROR H (RW)
MISSED UNCORRECTABLE ERROR H (RW)
PARITY ERROR H (RW)
MISSED PAR ERROR H (RW)
EDC SYNDROME 2 (RO)
EDC SYNDROME 0 (RO)
BC EDC ERROR (RO)
VALID (RO)
DIRTY (RO)
SHARED (RO)
CONTROL BIT PARITY (RO)
UNCORRECTABLE ERROR (RW)
MISSED UNCORRECTABLE ERROR (RW)
PARITY ERROR (RW)
MISSED PAR ERROR (RW)
Functions located elsewhere on the CPU module 97