Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. Table 30 (Cont.): B-Cache Correctable Error Address Register Description Field Description 16:0 B-CACHE MAP OFFSET [ read-only ] Cleared on power-up. Contains the last B-Cache MAP index. If a correctable EDC error has been detected, then the contents of this register are frozen until the BCCE ERROR bit in the BCCE Register has been cleared. If LW 2 or LW 0 has a correctable EDC error this field provides an address pointer into the B-Cache. 96 Functions located elsewhere on the <strong>CPU</strong> module
Copyright © 1993 Digital Equipment Corporation. 4.1.4.5 B-Cache Uncorrectable Error Register - CSR3 CSR offset = 6016 The B-Cache Uncorrectable Error Register latches the state of the B-Cache tag and control stores when a parity error or an EDC uncorrectable error (during the data portion of the cycle) is detected. The contents of B-Cache Uncorrectable Error Address Register are not updated while error flags are set, the lost error flag does not inhibit error logging. These errors are only detected by the B-Cache controller as a result of a processor masked write hit to a shared location, a LDxL or STxC, victimization of a cache location, or a System-bus READ, WRITE, or EXCHANGE transaction. (EDC errors are not detected by the Cobra Bus interface ASICs on LDxL, and System-bus WRITE transactions as a bystander or responder.) Figure 44: B-Cache Uncorrectable Error Register (BCUE) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 EDC SYNDROME 3 (RO) EDC SYNDROME 1 (RO) BC EDC ERROR (RO) UNCORRECTABLE ERROR H (RW) MISSED UNCORRECTABLE ERROR H (RW) PARITY ERROR H (RW) MISSED PAR ERROR H (RW) EDC SYNDROME 2 (RO) EDC SYNDROME 0 (RO) BC EDC ERROR (RO) VALID (RO) DIRTY (RO) SHARED (RO) CONTROL BIT PARITY (RO) UNCORRECTABLE ERROR (RW) MISSED UNCORRECTABLE ERROR (RW) PARITY ERROR (RW) MISSED PAR ERROR (RW) Functions located elsewhere on the <strong>CPU</strong> module 97
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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Page 61 and 62: Copyright © 1993 Digital Equipment
Page 99 and 100: CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
Page 103 and 104: Figure 41: B-Cache Control Register
Page 105 and 106: Table 28 (Cont.): B-Cache Control R
Page 107 and 108: Table 28 (Cont.): B-Cache Control R
Page 111: Copyright © 1993 Digital Equipment
Page 121 and 122: 4.3.1 Duplicate Tag Error Register
Page 123 and 124: 4.5 Lack of Cache Block Prefetch Co
Page 125 and 126: Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
Page 131 and 132: Table 38 (Cont.): System-bus Error
Page 133 and 134: 4.7.3 System-bus Error Address Low
Page 137 and 138: 4.8 Multiprocessor Configuration CS
Page 139 and 140: 4.9 System Interrupt Clear Register
Page 141 and 142: 4.10 Address Lock Register - CSR13
Page 143 and 144: 4.11 Miss Address Register - CSR14
Page 145 and 146: Table 46 (Cont.): C4 Revision Regis
Page 147 and 148: Table 48 (Cont.): Interval Timer In
Page 149 and 150: Table 50: D-bus Microcontroller Clo
Page 151 and 152: Figure 58: Granting Order rule 4 CP
Page 155 and 156: Table 54 (Cont.): BIU_CTL Field Des
Page 157 and 158: Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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