Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 29 (Cont.): B-Cache Correctable Error Register Description
Field Description
Undefined on power-up. EDC SYNDROME 1 is Valid when a correctable error has occurred.
This register is updated when the BCCE ERROR H bit is clear. The syndrome contained in this
register is relevant to longword 1 of data.
Refer to Table 25 for the single bit error syndrome list.
49 BC EDC ERROR [ read-only ]
Undefined on power-up. Valid when a correctable error has occurred to indicate that the CPU or
the B-Cache data was the cause of the error. When set the B-Cache was the cause of the data
error. This register is updated when the BCCE ERROR H bit is clear.
48:36 UNDEFINED [ read-only ]
Undefined
35 CORRECTABLE ERROR H [ read/write ]
Cleared on power-up, This must be cleared when CORRECTABLE ERROR is cleared. This bit will
not be set if a single bit error occurs when EDC correction is disabled. (The UNCORRECTABLE
ERROR bit will be set in CSR3.) Write ‘‘1’’ to clear.
34 MISSED CORRECTABLE ERROR H [ read/write ]
Cleared on power-up, This must be cleared when MISSED CORRECTABLE ERROR is cleared.
Write ‘‘1’’ to clear.
31:25 EDC SYNDROME 2 [ read-only ]
Undefined on power-up. Valid when a correctable error has occurred. This register is updated
when the BCCE ERROR bit is clear. The syndrome contained in this register is relevant to
longword 2 of data.
Refer to Table 25 for the single bit error syndrome list.
24:18 EDC SYNDROME 0 [ read-only ]
Undefined on power-up. Valid when a correctable error has occurred. This register is updated
when the BCCE ERROR bit is clear. The syndrome contained in this register is relevant to
longword 0 of data.
Refer to Table 25 for the single bit error syndrome list.
17 BC EDC ERROR [ read-only ]
Undefined on power-up. Valid when an correctable error has occurred to indicate that the CPU
or the B-Cache data was the cause of the error. When set the B-Cache was the cause of the
data error. This register is updated when the BCCE ERROR bit is clear.
11 VALID [ read-only ]
Cleared on power-up. Contains the value of the VALID bit for the last B-Cache location accessed
by the B-Cache controller. This register is updated when the BCCE ERROR bit is clear.
10 DIRTY [ read-only ]
Cleared on power-up. Contains the value of the DIRTY bit for the last B-Cache location accessed
by the B-Cache controller. This register is updated when the BCCE ERROR bit is clear.
9 SHARED [ read-only ]
Cleared on power-up. Contains the value of the SHARED bit for the last B-Cache location
accessed by the B-Cache controller. This register is updated when the BCCE ERROR bit is
clear.
8 CONTROL BIT PARITY [ read-only ]
Functions located elsewhere on the CPU module 93