Sable CPU Module Specification
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Sable CPU Module Specification

Sable CPU Module Specification Sable CPU Module Specification

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Copyright © 1993 Digital Equipment Corporation. 4.1.4.3 B-Cache Correctable Error Register - CSR1 CSR offset = 2016 The B-Cache Correctable Error Register latches the state of the B-Cache tag and control stores when a correctable EDC error (during the data portion of the cycle) is detected. The contents of B-Cache Correctable Error Address Register are not updated while error flags are set, lost error flags do not inhibit error logging. These errors are only detected as a result of a processor masked write hit to a shared location, victimization of a cache location, or a System-bus READ or EXCHANGE to a dirty location. Figure 42: B-Cache Correctable Error Register (BCCE) EDC SYNDROME 3 (RO) EDC SYNDROME 1 (RO) BC EDC ERROR (RO) UNDEFINED (RO) CORRECTABLE ERROR H (RW) MISSED CORRECTABLE ERROR H (RW) EDC SYNDROME 2 (RO) EDC SYNDROME 0 (RO) BC EDC ERROR (RO) VALID (RO) DIRTY (RO) SHARED (RO) CONTROL BIT PARITY (RO) CORRECTABLE ERROR (RW) MISSED CORRECTABLE ERROR (RW) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Table 29: B-Cache Correctable Error Register Description Field Description 63:57 EDC SYNDROME 3 [ read-only ] Undefined on power-up. EDC SYNDROME 3 is Valid when a correctable error has occurred. This register is updated when the BCCE ERROR H bit is clear. The syndrome contained in this register is relevant to longword 3 of data. Refer to Table 25 for the single bit error syndrome list. 56:50 EDC SYNDROME 1 [ read-only ] 92 Functions located elsewhere on the CPU module

Copyright © 1993 Digital Equipment Corporation. Table 29 (Cont.): B-Cache Correctable Error Register Description Field Description Undefined on power-up. EDC SYNDROME 1 is Valid when a correctable error has occurred. This register is updated when the BCCE ERROR H bit is clear. The syndrome contained in this register is relevant to longword 1 of data. Refer to Table 25 for the single bit error syndrome list. 49 BC EDC ERROR [ read-only ] Undefined on power-up. Valid when a correctable error has occurred to indicate that the CPU or the B-Cache data was the cause of the error. When set the B-Cache was the cause of the data error. This register is updated when the BCCE ERROR H bit is clear. 48:36 UNDEFINED [ read-only ] Undefined 35 CORRECTABLE ERROR H [ read/write ] Cleared on power-up, This must be cleared when CORRECTABLE ERROR is cleared. This bit will not be set if a single bit error occurs when EDC correction is disabled. (The UNCORRECTABLE ERROR bit will be set in CSR3.) Write ‘‘1’’ to clear. 34 MISSED CORRECTABLE ERROR H [ read/write ] Cleared on power-up, This must be cleared when MISSED CORRECTABLE ERROR is cleared. Write ‘‘1’’ to clear. 31:25 EDC SYNDROME 2 [ read-only ] Undefined on power-up. Valid when a correctable error has occurred. This register is updated when the BCCE ERROR bit is clear. The syndrome contained in this register is relevant to longword 2 of data. Refer to Table 25 for the single bit error syndrome list. 24:18 EDC SYNDROME 0 [ read-only ] Undefined on power-up. Valid when a correctable error has occurred. This register is updated when the BCCE ERROR bit is clear. The syndrome contained in this register is relevant to longword 0 of data. Refer to Table 25 for the single bit error syndrome list. 17 BC EDC ERROR [ read-only ] Undefined on power-up. Valid when an correctable error has occurred to indicate that the CPU or the B-Cache data was the cause of the error. When set the B-Cache was the cause of the data error. This register is updated when the BCCE ERROR bit is clear. 11 VALID [ read-only ] Cleared on power-up. Contains the value of the VALID bit for the last B-Cache location accessed by the B-Cache controller. This register is updated when the BCCE ERROR bit is clear. 10 DIRTY [ read-only ] Cleared on power-up. Contains the value of the DIRTY bit for the last B-Cache location accessed by the B-Cache controller. This register is updated when the BCCE ERROR bit is clear. 9 SHARED [ read-only ] Cleared on power-up. Contains the value of the SHARED bit for the last B-Cache location accessed by the B-Cache controller. This register is updated when the BCCE ERROR bit is clear. 8 CONTROL BIT PARITY [ read-only ] Functions located elsewhere on the CPU module 93

Copyright © 1993 Digital Equipment Corporation.<br />

4.1.4.3 B-Cache Correctable Error Register - CSR1<br />

CSR offset = 2016 The B-Cache Correctable Error Register latches the state of the B-Cache tag and<br />

control stores when a correctable EDC error (during the data portion of the cycle)<br />

is detected. The contents of B-Cache Correctable Error Address Register are not<br />

updated while error flags are set, lost error flags do not inhibit error logging.<br />

These errors are only detected as a result of a processor masked write hit to a shared<br />

location, victimization of a cache location, or a System-bus READ or EXCHANGE to<br />

a dirty location.<br />

Figure 42: B-Cache Correctable Error Register (BCCE)<br />

EDC SYNDROME 3 (RO)<br />

EDC SYNDROME 1 (RO)<br />

BC EDC ERROR (RO)<br />

UNDEFINED (RO)<br />

CORRECTABLE ERROR H (RW)<br />

MISSED CORRECTABLE ERROR H (RW)<br />

EDC SYNDROME 2 (RO)<br />

EDC SYNDROME 0 (RO)<br />

BC EDC ERROR (RO)<br />

VALID (RO)<br />

DIRTY (RO)<br />

SHARED (RO)<br />

CONTROL BIT PARITY (RO)<br />

CORRECTABLE ERROR (RW)<br />

MISSED CORRECTABLE ERROR (RW)<br />

6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1<br />

3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0<br />

Table 29: B-Cache Correctable Error Register Description<br />

Field Description<br />

63:57 EDC SYNDROME 3 [ read-only ]<br />

Undefined on power-up. EDC SYNDROME 3 is Valid when a correctable error has occurred.<br />

This register is updated when the BCCE ERROR H bit is clear. The syndrome contained in this<br />

register is relevant to longword 3 of data.<br />

Refer to Table 25 for the single bit error syndrome list.<br />

56:50 EDC SYNDROME 1 [ read-only ]<br />

92 Functions located elsewhere on the <strong>CPU</strong> module

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