Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 28 (Cont.): B-Cache Control Register Description
Field Description
Cleared on power-up. When set, READ transactions to address space 1 0000 0000 - 1 7FFF
FFFF are forced to return data from the corresponding CPU’s CSR8-CBEAL register. When set,
memory WRITE allocate transactions are not supported, however CSR write transactions are
supported. This causes the transactions to the System-bus reserved memory address space to
supply a know pattern, which is the transaction address as it appears on the System-bus, to fill
into the B-Cache. For a CPU commander, the CSR data will be filled to the B-Cache tag and
data entry indexed by the transaction physical address as follows :
INDEX TAG FILLED WITH ADDRESS BITS
for 1MB cache
for 4MB cache
Also, when this bit is set, the tag probe at the transaction address is forced clean to avoid victims,
and if bits and ENB ALLOCATE are also set the B-Cache tag control bits are filled
with the value specified in bits of this register correct parity unless parity is forced bad,
regardless of the state of bit and the returned data is written into the B-Cache data store.
Refer to Section 9.2 for the actual returned data format.
10 DIS BLOCK WRITE AROUND [ read/write ]
Cleared on power-up. When clear only masked processor writes result in allocation, full block -
unmasked writes will write around the B-Cache and not result in allocation. When set processor
writes result in allocation regardless of the block mask.
9 ENB B-CACHE COND I/O UPDATES [ read/write ]
Cleared on power-up. When set, Conditional updates of of the B-Cache will occur due to Systembus
writes when the I/O module is the commander. A System-bus write will cause an update
if both the contents of the duplicate tag store and the B-Cache indicate a hit. When clear,
Unconditional updates of the B-Cache will occur when a System-bus write hits a VALID B-Cache
location when the I/O module is the System-bus commander. Refer to Chapter 6 and Section 4.3
for further details about conditional invalidation and updating.
8 ENB EDC CHK [ read/write ]
Cleared on power-up. When set, the EDC of the B-CACHE Data Store and processor written
data will be checked. EDC will be checked by the B-Cache controller only when a System-bus
READ or EXCHANGE hits Dirty, a masked write to a shared location occurs, or during a victim
write. When clear, checking for single and multiple bit errors is disabled, but EDC generation still
occurs.
7 ENB EDC CORRECTION [ read/write ]
Cleared on power-up to disable EDC correction of data during any transaction, even correctable
single bit errors are reported as uncorrectable. When set, enables EDC correction of processor
write data, victim data, and dirty read hit data.
6 ENB COR ERR INTERRUPT [ read/write ]
Cleared on power-up. When set, EDC correctable errors detected during any transaction that
is logged by CSR1 will result in the assertion of the HARDWARE ERROR INTERRUPT. When
clear the interrupt is not sent but error information is captured in CSR1.
5 FILL WRONG DUP TAG STORE PAR [ read/write ]
Cleared on power-up. When set, the wrong parity value will be written in the Primary D-Cache
duplicate tag store parity location when a primary D-Cache location is updated during a processor
primary D-cache allocation. This bit is NOT self clearing. When this bit is set, the ENB TAG &
DUP TAG PAR CHK bits 34 and 2 should be cleared; otherwise a HARDWARE ERROR interrupt
will be signaled every time the duplicate tag store is written.
90 Functions located elsewhere on the CPU module