Sable CPU Module Specification

Table 28 (Cont.): B-Cache Control Register Description
Field Description
Copyright © 1993 Digital Equipment Corporation.
Cleared on power-up, These bits must be correctly set before the B-Cache is accessed.
• 1 - 4MB Cache
• 0 - 1MB Cache
The value of this field controls not only which tag signals are used in determining the proper
parity value for the tag, but also in determining whether address bits 21 and 20 should be driven
by the Cobra Bus interface ASICs during access to the B-Cache.
29:16 EDC L [ read/write ]
Cleared on power-up, When the FORCE EDC/CONTROL bit 12 is set during B-Cache initialization,
the values specified into this register are written forced on the EDC field of longwords 2 and
0 of any filled B-Cache locations. Refer to Section 9.2 for further details.
15:13 SHARED,DIRTY,VALID [ read/write ]
Cleared on power-up, When the FORCE EDC/CONTROL bit is set during B-Cache initialization,
the values specified in here in SHARED,DIRTY, and VALID will be filled into the control field of
the B-Cache location referenced by a READ_BLOCK. Refer to Section 9.2 for further details.
When FORCE EDC/CONTROL is cleared these bits have no effect.
12 FORCE EDC/CONTROL [ read/write ]
Cleared on power-up. Attention to the state of bits should be given when setting this
bit, to avoid machine check responses. When set, for every processor READ_BLOCK cycle
to a cacheable location the appropriate B-Cache location (indicated by address bits ) is
updated as follows:
1. Tag Probe at READ_BLOCK address is forced clean, to avoid victims.
2. The value of address bits with its associated parity is filled into the B-Cache tag
store.
3. The value of the control bits specified in this register’s SHARED,DIRTY, and VALID and
their associated parity are filled into the B-Cache control store, and the EDC bits specified
here in EDC H and L are filled into the EDC field of the data store.
4. The B-Cache is updated with the data returned on the System-bus or the CSR data if the
ENB B-CACHE INIT bit is set. This data is also returned to the processor to satisfy
the READ BLOCK request.
This bit is NOT self clearing. Refer to Section 9.2 for further details.
11 ENB B-CACHE INIT [ read/write ]
Functions located elsewhere on the CPU module 89