Sable CPU Module Specification

Figure 41: B-Cache Control Register (BCC)
CACHE SIZE H (RW)
EDC H (RW)
S,D,V H (RW)
FORCE EDC/CONTROL H (RW)
ENB B-CACHE INIT H (RW)
DIS BLOCK WRITE AROUND H (RW)
ENB B-CACHE COND I/O UPDATES H (RW)
ENB EDC CHK H (RW)
ENB EDC CORRECTION H (RW)
ENB COR ERR INTERRUPT H (RW)
FILL WRONG DUP TAG STORE PAR H (RW)
FILL WRONG CONTROL PAR H (RW)
FILL WRONG TAG PAR H (RW)
ENB TAG & DUP TAG PAR CHK H (RW)
FORCE FILL SHARED H (RW)
ENB ALLOCATE H (RW)
CACHE SIZE (RW)
EDC L (RW)
SHARED,DIRTY,VALID (RW)
FORCE EDC/CONTROL (RW)
ENB B-CACHE INIT (RW)
DIS BLOCK WRITE AROUND (RW)
ENB B-CACHE COND I/O UPDATES (RW)
ENB EDC CHK (RW)
ENB EDC CORRECTION (RW)
ENB COR ERR INTERRUPT (RW)
FILL WRONG DUP TAG STORE PAR (RW)
FILL WRONG CONTROL PAR (RW)
FILL WRONG TAG PAR (RW)
ENB TAG & DUP TAG PAR CHK (RW)
FORCE FILL SHARED (RW)
ENB ALLOCATE (RW)
Copyright © 1993 Digital Equipment Corporation.
6666555555555544
4444444433333333
3322222222221111
111111
3210987654321098
7654321098765432
1098765432109876
5432109876543210
Functions located elsewhere on the CPU module 87