Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. 4.1.4.2 B-Cache Control Register - CSR0 CSR offset = 0016 The B-Cache Control Register contains all of the control fields to enable/disable various functions of the B-Cache. This register is provided primarily for the use of diagnostic self test code running at system initialization time. NOTE: The CPU shall ensure that the state of control flags in the low longword are consistent with control flags in the upper longword by performing quadword writes. 86 Functions located elsewhere on the CPU module
Figure 41: B-Cache Control Register (BCC) CACHE SIZE H (RW) EDC H (RW) S,D,V H (RW) FORCE EDC/CONTROL H (RW) ENB B-CACHE INIT H (RW) DIS BLOCK WRITE AROUND H (RW) ENB B-CACHE COND I/O UPDATES H (RW) ENB EDC CHK H (RW) ENB EDC CORRECTION H (RW) ENB COR ERR INTERRUPT H (RW) FILL WRONG DUP TAG STORE PAR H (RW) FILL WRONG CONTROL PAR H (RW) FILL WRONG TAG PAR H (RW) ENB TAG & DUP TAG PAR CHK H (RW) FORCE FILL SHARED H (RW) ENB ALLOCATE H (RW) CACHE SIZE (RW) EDC L (RW) SHARED,DIRTY,VALID (RW) FORCE EDC/CONTROL (RW) ENB B-CACHE INIT (RW) DIS BLOCK WRITE AROUND (RW) ENB B-CACHE COND I/O UPDATES (RW) ENB EDC CHK (RW) ENB EDC CORRECTION (RW) ENB COR ERR INTERRUPT (RW) FILL WRONG DUP TAG STORE PAR (RW) FILL WRONG CONTROL PAR (RW) FILL WRONG TAG PAR (RW) ENB TAG & DUP TAG PAR CHK (RW) FORCE FILL SHARED (RW) ENB ALLOCATE (RW) Copyright © 1993 Digital Equipment Corporation. 6666555555555544 4444444433333333 3322222222221111 111111 3210987654321098 7654321098765432 1098765432109876 5432109876543210 Functions located elsewhere on the CPU module 87
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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Page 51 and 52: Copyright © 1993 Digital Equipment
Page 99 and 100: CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
Page 101: Copyright © 1993 Digital Equipment
Page 105 and 106: Table 28 (Cont.): B-Cache Control R
Page 107 and 108: Table 28 (Cont.): B-Cache Control R
Page 121 and 122: 4.3.1 Duplicate Tag Error Register
Page 123 and 124: 4.5 Lack of Cache Block Prefetch Co
Page 125 and 126: Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
Page 131 and 132: Table 38 (Cont.): System-bus Error
Page 133 and 134: 4.7.3 System-bus Error Address Low
Page 137 and 138: 4.8 Multiprocessor Configuration CS
Page 139 and 140: 4.9 System Interrupt Clear Register
Page 141 and 142: 4.10 Address Lock Register - CSR13
Page 143 and 144: 4.11 Miss Address Register - CSR14
Page 145 and 146: Table 46 (Cont.): C4 Revision Regis
Page 147 and 148: Table 48 (Cont.): Interval Timer In
Page 149 and 150: Table 50: D-bus Microcontroller Clo
Page 151 and 152: Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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