Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
checking is performed whenever the processor hits the cache on a read and error
checking and possibly correcting is performed whenever a System-bus read probe
hits dirty, the victimization of a dirty location, or a masked processor write to a
shared location. For details regarding EDC error detection refer to Chapter 8.
4.1.4 B-Cache Control Register Definitions
The B-Cache subsystem is manipulated at separate times by two different controllers.
The first is the processor which will probe the tag field, and if hit, will read or
write data into the B-Cache. The behavior of the processor relative to the B-Cache
is controlled or monitored by the processors BIU_STAT, BIU_ADDR, FILL_ADDR,
BIU_CTL, AND BC_TAG internal processor registers. For a description of these
registers refer to the Section 3.9.3.
The second is the B-Cache controller that processes all miss traffic and System-bus
probe activity. The behavior of the B-Cache controller is determined by the settings
of the B-Cache CSR’s defined below.
4.1.4.1 CSR Space
There exists primary and secondary CSR space. Primary CSR space is used by Sable
systems, secondary CSR space is used by Cobra systems.
Sable CPUs recognize only primary CSR space. What follows is a list of base addresses
for the CPUs.
Table 27: Base Addresses for CSRs
CPU Base Address
CPU0
CPU1
CPU2
CPU3
3.8000.0000
3.8100.0000
3.8200.0000
3.8300.0000
Functions located elsewhere on the CPU module 85