Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 26:
Flag Description
VALID When set indicates that the data found in the other bits of the control store, the tag store,
and the data store contain valid information. The VALID bit is set only by the B-Cache
controller when a cache block is filled with new data. The VALID bit is cleared only by the
B-Cache controller when a System-bus write requires a cache block invalidation.
DIRTY When set (and VALID bit set) indicates that the data store contains an updated copy of a
main memory location. This cache data must be written back to main memory when the
cache location is victimized. At most, in a Cobra system, there will be only one copy of any
given memory location marked DIRTY. The DIRTY bit is set by the processor performing
a Fast B-Cache write hit cycle, or by the B-Cache assisting the processor perform a STxC
cycle. When the VALID bit is cleared the B-Cache controller will guarantee that the DIRTY
bit is also cleared.
SHARED When set (and VALID bit set) indicates that the data store contains a copy of a main
memory location that another System-bus node also has a copy of. Writes to this location
must ‘‘write-through’’ the cache so that a coherent view of memory is maintained. The
SHARED bit is set by the B-Cache controller when the System-bus CSHARED_L signal
is asserted during cache block allocation or when a System-bus read hits a location found
in the B-Cache (CSHARED_L must be pulled). The SHARED bit is cleared by the B-
Cache controller when it performs a System-bus WRITE and the CSHARED_L signal isn’t
asserted. When the VALID bit is cleared the B-Cache controller guarantees that the DIRTY
bit is also cleared.
PARITY Contains EVEN parity over the contents of the Control Store. The PARITY is valid even if
the VALID bit is not set. Parity is checked by the processor during every B-Cache probe
cycle, and by the B-Cache controller during every System-bus initiated probe cycle. For
details regarding parity error detection refer to Chapter 8.
4.1.2 Tag Store
The Tag Store contains the high order address bits ( for a 4 MB
cache) of the memory location that currently resides in the cache entry. There is a
single parity bit that provides EVEN parity over the complete Tag Store. Once powerup
initialization has occurred, the parity bit will contain valid parity regardless of
the value of the Control Stores VALID bit.
Parity is checked by the processor during every B-Cache probe cycle, and by the B-
Cache controller during every System-bus initiated probe cycle. For details regarding
parity error detection refer to Chapter 8.
4.1.3 Data Store
The Data Store contains the actual data of the memory location that is ‘‘cached’’.
Every cache entry is made up of 8 longwords each longword protected by 7 bits of
EDC. Physically the cache is only 4 longwords wide, so a cache block consists of 2
consecutive addresses aligned on a 32 byte block boundary. After initialization, the
EDC bits are valid regardless of the validity of the Control Store’s VALID bit. Error
84 Functions located elsewhere on the CPU module