Sable CPU Module Specification
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Sable CPU Module Specification

Sable CPU Module Specification Sable CPU Module Specification

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C.8.1 21064 Error Flows .......................................... 239 C.8.1.1 EDC Error Handling . . . ................................... 239 C.8.1.1.1 Single Bit I-stream EDC error . . .......................... 239 C.8.1.1.2 Single Bit D-stream EDC error . . .......................... 240 C.8.1.1.3 Double Bit I-stream EDC error . . .......................... 240 C.8.1.1.4 Double Bit D-stream EDC error . .......................... 240 C.8.1.2 BIU: tag address parity error ................................ 241 C.8.1.3 BIU: tag control parity error ................................ 241 C.8.1.4 BIU: system transaction terminated with CACK_HERR . .......... 241 C.8.2 Response to Multiple Errors ................................... 241 Appendix D REVISION HISTORY .................................. 243 INDEX EXAMPLES 1 Update vs Invalidate Algorithm ................................ 104 FIGURES 1 Sable CPU Module Block Diagram .............................. 2 2 C4 Chip Block Diagram ....................................... 3 3 21064 CPU Chip Block Diagram ................................ 4 4 CPU Form Factors .......................................... 8 5 TB_TAG_FIG ............................................... 17 6 ITB_PTE .................................................. 18 7 ICCSR . ................................................... 19 8 ITB_PTE_TEMP . ........................................... 21 9 EXC_ADDR ................................................ 22 10 SL_CLR ................................................... 23 11 SL_RCV ................................................... 24 12 PS ....................................................... 25 13 EXC_SUM ................................................. 26 14 PAL_BASE ................................................ 28 15 HIRR . . ................................................... 29 16 SIRR . . ................................................... 31 17 ASTRR ................................................... 32 18 HIER . . ................................................... 33 19 SIER . . ................................................... 34 20 ASTER ................................................... 35 21 SL_XMIT .................................................. 36 22 TB_CTL_FIG ............................................... 38 23 DTB_PTE ................................................. 39 24 DTB_PTE_TEMP ........................................... 40 x

25 MM_CSR .................................................. 41 26 DECchip 21064 ABOX_CTL ................................... 43 27 DECchip 21064-A275 ABOX_CTL ............................... 44 28 ALT_MODE ................................................ 46 29 BIU Control Register (BIU_CTL) ............................... 47 30 DECchip 21064-A275 BIU Control Register (EV45_BIU_CTL) ......... 50 31 Integer Operate Pipeline . . . ................................... 60 32 Memory Reference Pipeline . ................................... 60 33 Floating Point Operate Pipeline ................................ 61 34 Producer-Consumer Latency Matrix . . . .......................... 66 35 DECchip 21064 C_STAT . . . ................................... 71 36 DECchip 21064-A275 C_STAT .................................. 71 37 BIU_STAT ................................................. 74 38 Fill Syndrome . . . ........................................... 78 39 BC_TAG .................................................. 80 40 Back-up Cache Entry ........................................ 83 41 B-Cache Control Register (BCC) ................................ 87 42 B-Cache Correctable Error Register (BCCE) ....................... 92 43 B-Cache Correctable Error Address Register (BCCEA) ............... 95 44 B-Cache Uncorrectable Error Register (BCUE) . . . .................. 97 45 B-Cache Uncorrectable Error Address Register (BCUEA) . . . .......... 100 46 Duplicate Tag Error Register (DTER) . . .......................... 105 47 System-bus Control Register (CBCTL) . .......................... 108 48 System-bus Error Register (CBE) ............................... 112 49 System-bus Error Address Low Register (CBEAL) .................. 117 50 System-bus Error Address High Register (CBEAH) ................. 118 51 Processor Mailbox Register (PMBX) . . . .......................... 121 52 Interprocessor Interrupt Request Register (IPIR) . .................. 122 53 System Interrupt Clear Register (SIC) . .......................... 123 54 Address Lock Register (ADLK) ................................. 125 55 Miss Address Register Low (MADRL) . . .......................... 127 56 C4 Revision Register (CRR) . ................................... 128 57 The 21064 Serial Load Data Format . . . .......................... 131 58 Granting Order . . ........................................... 135 59 FAST EXTERNAL CACHE READ HIT . .......................... 147 60 FAST EXTERNAL CACHE WRITE HIT .......................... 148 61 READ BLOCK TRANSACTION ................................ 149 62 WRITE BLOCK . . ........................................... 151 63 BARRIER TRANSACTION . ................................... 153 64 FETCH TRANSACTION . . . ................................... 154 65 Address Space Map .......................................... 156 66 LDQ Data Format (LDQ_DF) .................................. 190 67 System backplane clocks . . . ................................... 206 68 module clocks . . . ........................................... 207 69 Module Layup (reference) . . ................................... 210 xi

C.8.1 21064 Error Flows .......................................... 239<br />

C.8.1.1 EDC Error Handling . . . ................................... 239<br />

C.8.1.1.1 Single Bit I-stream EDC error . . .......................... 239<br />

C.8.1.1.2 Single Bit D-stream EDC error . . .......................... 240<br />

C.8.1.1.3 Double Bit I-stream EDC error . . .......................... 240<br />

C.8.1.1.4 Double Bit D-stream EDC error . .......................... 240<br />

C.8.1.2 BIU: tag address parity error ................................ 241<br />

C.8.1.3 BIU: tag control parity error ................................ 241<br />

C.8.1.4 BIU: system transaction terminated with CACK_HERR . .......... 241<br />

C.8.2 Response to Multiple Errors ................................... 241<br />

Appendix D REVISION HISTORY .................................. 243<br />

INDEX<br />

EXAMPLES<br />

1 Update vs Invalidate Algorithm ................................ 104<br />

FIGURES<br />

1 <strong>Sable</strong> <strong>CPU</strong> <strong>Module</strong> Block Diagram .............................. 2<br />

2 C4 Chip Block Diagram ....................................... 3<br />

3 21064 <strong>CPU</strong> Chip Block Diagram ................................ 4<br />

4 <strong>CPU</strong> Form Factors .......................................... 8<br />

5 TB_TAG_FIG ............................................... 17<br />

6 ITB_PTE .................................................. 18<br />

7 ICCSR . ................................................... 19<br />

8 ITB_PTE_TEMP . ........................................... 21<br />

9 EXC_ADDR ................................................ 22<br />

10 SL_CLR ................................................... 23<br />

11 SL_RCV ................................................... 24<br />

12 PS ....................................................... 25<br />

13 EXC_SUM ................................................. 26<br />

14 PAL_BASE ................................................ 28<br />

15 HIRR . . ................................................... 29<br />

16 SIRR . . ................................................... 31<br />

17 ASTRR ................................................... 32<br />

18 HIER . . ................................................... 33<br />

19 SIER . . ................................................... 34<br />

20 ASTER ................................................... 35<br />

21 SL_XMIT .................................................. 36<br />

22 TB_CTL_FIG ............................................... 38<br />

23 DTB_PTE ................................................. 39<br />

24 DTB_PTE_TEMP ........................................... 40<br />

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