Schaltungstechnik

8.1 Zur Charakterisierung einer Logikfunktion 545
library IEEE;
use IEEE.std_logic_1164.all;
entity DFF_tb is
end DFF_tb;
architecture DFF_tb_arch of DFF_tb is
signal PR : std_logic := '0';
signal CL : std_logic := '1';
signal CLK: std_logic := '1';
signal D : std_logic := '0';
signal Q : std_logic;
signal NQ : std_logic;
signal tdef: time :=50ns;
signal tper: time :=200ns;
component dff_1
Port (PR : IN std_logic;
CL : IN std_logic;
CLK: IN std_logic;
D : IN std_logic;
Q : OUT std_logic;
NQ: OUT std_logic);
end Component;
begin
U_DFF : dff_1
port map (PR => PR,
CL => CL,
CLK => CLK,
D => D,
Q => Q,
NQ => NQ);
clock_mod: process
begin
CLK