Einführung in Computer Microsystems

) Operand 1: Control=0 und Daten=Adresse von Operand 1 im RAM.
c) Operand 2: Control=0 und Daten=Adresse von Operand 2 im RAM.
d) Ergebnis: Control=0 und Daten=Adresse im RAM an die das Ergebnis geschrieben werden soll.
Die mitgelieferte Testbench enthält jeweils einen Test für die Addition und für die Multiplikation. Nach der Addition sollte an
ram(6) = 006911 16 stehen. Bei der Multiplikation entsprechend ram(6) = 010B81 16 .
Der Automat für die Kommunikation für den FSL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.datatypes.all;
entity fsl is
Port(
-- Bus protocol ports , do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 7);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end fsl;
architecture Behavioral of fsl is
component fsm is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
op1_addr : in type_wd_addr;
op2_addr : in type_wd_addr;
result_addr : in type_wd_addr;
operation : in operation_type;
start : in STD_LOGIC;
ready : out STD_LOGIC);
end component fsm;
for all: fsm use entity work.fsm(Behavioral);
type fsl_state_type is (WAIT_READY , CMD , OP1 , OP2 , RES , WAIT_READY_ZERO);
signal r_op1 : type_wd_addr;
signal r_op2 : type_wd_addr;
signal r_res : type_wd_addr;
signal r_operation : operation_type;
signal r_start : STD_LOGIC;
signal r_ready : STD_LOGIC;
signal r_read : STD_LOGIC;
signal FSL_STATE : fsl_state_type;
begin
component_fsm : fsm port map(
clock => FSL_Clk ,
reset => FSL_Rst ,
op1_addr => r_op1 ,
op2_addr => r_op2 ,
result_addr => r_res ,
operation => r_operation ,
start => r_start ,
ready => r_ready
);
FSL_S_Read