Abstract-Band - Fakultät für Informatik, TU Wien - Technische ...

Institut für Technische Informatik
Arbeitsbereich Embedded Computing Systems
Andreas Hagmann
Performance Aware Hardware Runtime Monitors
Studium: Masterstudium Technische Informatik
BetreuerIn: Ao.Univ.Prof. Dr. Andreas Steininger
The field of research for runtime verification (RV) deals with verification
methods, classified between common testing and formal verification. In a RV
setting, the system under test (SUT) is observed by a runtime monitor that
checks the monitored behaviour against a specification. Based on existing
approaches, this thesis presents a RV framework, capable of observing embedded
real-time systems. The proposed framework features a runtime monitoring
unit, implemented as micro-processor architecture. The monitoring unit
is built entirely in hardware and may be used stand-alone or integrated in the
target system. It evaluates claims, specified as atomic propositions, Linear
Temporal Logic, and Metric Temporal Logic formulas. The connection to the
system under test is established by wire-taping its external interfaces. After an
introduction to RV methods, this thesis captures the state-of-the-art and
provides theoretical background. It proceeds with an analysis of existing parts
and proposes optimizations on them. Thereby, the influence of different
improvements is compared and verified by benchmarks, conducted with a
software model of the runtime verification unit. Furthermore, the runtime verification
framework is extended to support natively the evaluation of future
time temporal formulas. A prototype implementation, shows the feasibility of
the novel approach. The design of the RV unit is done with special focus on
not influencing the behaviour of the SUT and getting along with the limited
resources available within embedded systems. Benchmark results compare the
improved runtime verification unit to the existing design and show a speed up
factor of twelve. Synthesis runs show, that the proposed design fits well into a
low-end commercial off-the-shelf FPGA. A case study completes this thesis and
demonstrates the benefit of a RV unit within a real-world Unmanned Aerial
System to detect erroneous sensor readings.
6
Markus Hofstätter
Solving the Labeling Problem: A Byzantine Fault-Tolerant Self-Stabilizing FPGA
Protoptye based on the FATAL+ Protocol
Studium: Masterstudium Technische Informatik
BetreuerIn: Univ.Prof. Dr. Ulrich Schmid
The topic of this thesis lies in the intersection of VLSI design and fault-tolerant
distributed algorithms. It is devoted to the development of an FPGA implemen-