Gecko3 - CCC Event Weblog

E.1. Firmware
#define f i l e s i z e 130952 // f i l e s i z e f o r XC3S200 ( important : you must a d j u s t t h i s
s i z e f o r o t h e r d e v i c e s )
#define DONE 0 x41 // vendor r e q u e s t t h a t DONE b i t i s s e t
25
extern BOOL fpga cfg m ode ; // e x t e r n a l v a r i a b l e f o r r e s e t FPGA c o n f i g u r a t i o n mode
extern BOOL done ack ; // e x t e r n a l v a r i a b l e f o r send vendor r e q u e s t DONE
acknoledgement
extern BYTE timer ; // timer v a l u e from timeout timer
30 void G p i f I n i t ( void ) ; // f u n c t i o n p r o t o t y p e from g p i f . c
BOOL busy ; // busy f l a g
unsigned long counter = 0 ; // b y t e counter
35 void f p g a c f g i n i t ( void )
{
IFCONFIG = 0xC0 ;
// IFCLKSRC=1 , FIFOs e x e c u t e s on i n t e r n a l c l k source
// xMHz=1 , 48MHz i n t e r n a l c l k r a t e
40 // IFCLKOE=0 , Don ’ t d r i v e IFCLK pin s i g n a l at 48MHz
// IFCLKPOL=0 , Don ’ t i n v e r t IFCLK pin s i g n a l from i n t e r n a l c l k
// ASYNC=0 , s l a v e FIFOs o p e r a t e synchronously
// GSTATE=0 , d i s a b l e GPIF s t a t e s out on PORTE[ 2 : 0 ]
// IFCFG[ 1 : 0 ] = 0 0 , FX2 in p o r t s mode
45 GPIFABORT = 0xFF ; // a b o r t any waveforms pending
GPIFCTLCFG = 0 ; // TRICTL = 0 , CTL 0 . . 2 as CMOS, Not T r i s t a t a b l e
SYNCDELAY;
OEB = 0xFF ; // Port B a l l p i n s as output
IOB = 0 ; // Set i n i t a l i s a t i o n f o r Port B
50 OEA &= 0xEF ; // Port A b i t 4 as i n p u t f o r I n i t B
OEA |= 0 x20 ; // Port A b i t 5 as output f o r Prog B
PA5 = 1 ; // Set i n i t a l i s a t i o n f o r Prog B
OEA &= 0x7F ; // Port A b i t 7 as i n p u t f o r Done
}
55
void f p g a c f g ( void )
{
WORD count , i ;
60 GPIFIDLECTL &= 0xF9 ; // b r i n g CS B , RDWR B low
PA5 = 0 ; // b r i n g Prog B low b r i n g s t h e d e v i c e in t h e i n i t a l i s a t i o n mode
// and h o l d i t t h e r e
PA5 = 1 ; // b r i n g Prog B b i t h i g h
65
while (PA4 == 0) // i f I n i t B goes h i g h t h e d e v i c e i s in t h e c o n f i g u r a t i o n
l o a d mode
{
;
}
70 TR0 = 1 ; // e n a b l e Timer 0 f o r Timeout
while ( counter < f i l e s i z e )
{
i f ( timer == 61) // 61 timer o v e r f l o w s accord ca . 1 second
{
75 break ; // t h e timeout a b o r t t h e r o u t i n e
}
i f ( ! ( EP2468STAT & bmEP2EMPTY) ) // check EP2 EMPTY( busy ) b i t in EP2468STAT (SFR) ,
core s e t ’ s t h i s b i t when FIFO i s empty
{
// a u t o p o i n t e r source a d r e s s from EP2OUT
80 AUTOPTRH1 = MSB( &EP2FIFOBUF ) ;
AUTOPTRL1 = LSB( &EP2FIFOBUF ) ;
count = (EP2BCH