Gecko3 - CCC Event Weblog

E.1. Firmware
unsigned long s p i f l a s h a d r e s s =0;
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
// Task Dispatcher hooks
81 // The f o l l o w i n g hooks are c a l l e d by t h e t a s k d i s p a t c h e r .
//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
void G p i f I n i t ( void ) ; // f u n c t i o n p r o t o t y p e from g p i f . c
void TD Init ( void ) // C a l l e d once at s t a r t u p
86 {
// s e t t h e CPU c l o c k to 48MHz
CPUCS = ( (CPUCS & ˜bmCLKSPD) | bmCLKSPD1) ;
SYNCDELAY;
91 EP1OUTCFG = 0xA0 ; // always OUT, v a l i d , b u l k
EP1INCFG = 0xA0 ; // always IN , v a l i d , b u l k
SYNCDELAY;
EP2CFG = 0xA2 ; // EP2OUT, bulk , s i z e 512 , 2x b u f f e r e d
SYNCDELAY;
96 EP4CFG = 0xE0 ; // EP4IN , bulk , s i z e 512 , 2x b u f f e r e d
SYNCDELAY;
EP6CFG = 0xA2 ; // EP6OUT, bulk , s i z e 512 , 2x b u f f e r e d
SYNCDELAY;
EP8CFG = 0xE0 ; // EP8IN , bulk , s i z e 512 , 2x b u f f e r e d
101 SYNCDELAY;
// out e n d p o i n t s do not come up armed
// s i n c e t h e d e f a u l t s are d o u b l e b u f f e r e d we must w r i t e dummy b y t e counts t w i c e
SYNCDELAY;
106 EP2BCL = 0 x80 ; // arm EP2OUT by w r i t i n g b y t e count w/ s k i p .
SYNCDELAY;
EP2BCL = 0 x80 ;
SYNCDELAY;
111 FIFORESET = 0 x80 ; // s e t NAKALL b i t to NAK a l l t r a n s f e r s from h o s t
/∗SYNCDELAY;
FIFORESET = 0 x02 ; // r e s e t EP2 FIFO
SYNCDELAY;
FIFORESET = 0 x04 ; // r e s e t EP4 FIFO
116 SYNCDELAY; ∗/
FIFORESET = 0 x06 ; // r e s e t EP6 FIFO
SYNCDELAY;
FIFORESET = 0 x08 ; // r e s e t EP8 FIFO
SYNCDELAY;
121 FIFORESET = 0 x00 ; // c l e a r NAKALL b i t to resume normal o p e r a t i o n
SYNCDELAY;
EP6FIFOCFG = 0 x00 ; // a l l o w core to see zero to one t r a n s i t i o n o f auto out b i t
SYNCDELAY;
126 EP6FIFOCFG = 0 x10 ; // auto out mode , d i s a b l e PKTEND zero l e n g t h send , b y t e ops
SYNCDELAY;
EP8FIFOCFG = 0 x08 ; // auto in mode , d i s a b l e PKTEND zero l e n g t h send , b y t e ops
SYNCDELAY;
EP1OUTBC = 0 x00 ; // arm EP1OUT by w r i t i n g any v a l u e to EP1OUTBC r e g i s t e r
131
s p i f l a s h i n i t ( ) ; // i n i t i a l i z e Port A [ 0 : 3 ] ( f u n c t i o n in s p i f l a s h r d w r f u n c . c )
f p g a c f g i n i t ( ) ; // i n i t i a l i z e Port A [ 4 : 7 ] , Port B and CTL0 f o r FPGA
c o n f i g u r a t i o n ( f u n c t i o n in f p g a c f g f u n c . c )
b o o t l o a d c f g ( ) ; // s t a r t l o a d i n g FPGA c o n f i g u r a t i o n from SPI Flash in FPGA
( f u n c t i o n in s p i f l a s h r d w r f u n c . c )
136 G p i f I n i t ( ) ; // i n i t i a l i z e GPIF r e g i s t e r s ( f u n c t i o n in g p i f . c )
EZUSB InitI2C ( ) ;
//PORTACFG = bmINT0 ; // PA0 t a k e s on INT0/ a l t e r n a t e f u n c t i o n
Project Report 65