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E. Quellcode
∗ Author : Matthias Zurbrügg
∗ Date o f c r e a t i o n : 22.11.2006
∗ D e s c r i p t i o n :
16 ∗ Source code o f Cypress EZ−USB FX2 Firmware
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#include ” fx2 . h”
21 #include ” f x 2 r e g s . h”
#include ” f x 2 s d l y . h” // SYNCDELAY macro , see S e c t i o n 15.14 o f FX2 Tech .
// Ref . Manual f o r usage d e t a i l s .
#include ” g p i f r d w r f u n c . h”
#include ” s p i f l a s h r d w r f u n c . h”
26 #include ” f p g a c f g f u n c . h”
#include ” eeprom rd wr func . h”
// firmware v e r s i o n (max t h r e e d i g i t s )
#define f w v e r d i g i t 0 ’ 1 ’
31 #define f w v e r d i g i t 1 ’ . ’
#define f w v e r d i g i t 2 ’ 0 ’
#define f w v e r d i g i t 3 ’ 1 ’
// Cypres b i t masks
36 #define bmEP0BSY 0 x01
#define bmEP1OUTBSY 0 x02
#define bmEP1INBSY 0 x04
// Defines f o r EEPROM communications
41 #define w r i t e n o k 1
#define w r i t e o k 0
#define read nok 1
#define read ok 0
#define i n i t 0
46 #define i d l e 3
// Cypres v a r i a b l e s
extern BOOL GotSUD ; // Received s e t u p data f l a g
extern BOOL S l e e p ;
51 extern BOOL Rwuen ;
extern BOOL S e l f p w r ;
BYTE C o n f i g u r a t i o n ; // Current c o n f i g u r a t i o n
BYTE A l t e r n a t e S e t t i n g ; // A l t e r n a t e s e t t i n g s
56
// V a r i a b l e s f o r GPIF communications
BOOL i n e n a b l e = FALSE ; // f l a g to e n a b l e IN t r a n s f e r s
BOOL f i f o r d e n a b l e = FALSE; // f l a g to e n a b l e GPIF FIFO READ Transaction
BOOL f i f o r d i n t = FALSE; // GPIF FIFO READ Transaction i n t e r r u p t f l a g
61 BOOL enum high speed = FALSE; // f l a g to l e t firmware know FX2 enumerated at
h i g h speed
// V a r i a b l e s f o r EEPROM coummunications
BOOL eeprom write mode = FALSE; // s e t eeprome write mode to f a l s e
BOOL s t a r t t r a n s a c t i o n = 1 ;
BOOL eeprom read mode = FALSE;
66 BYTE e e p r o m r e a d s t a t e = i d l e ; // s e t eeprom read s t a t e on i d l e
WORD eeprom adress = 0 ;
WORD r e a d c o u n t = 0 ; // v a l u e o f number o f b y t e s to read
// V a r i a b l e s f o r FPGA c o n f i g u r a t i o n
BOOL fpga cfg m ode = FALSE; // FPGA c o n f i g u r a t i o n mode v a r i a b l e
71 BOOL done ack = FALSE ; // v a r i a b l e to g i v e vendor r e q u e s t DONE
acknoledgement
// V a r i a b l e s f o r SPI Flash communications
BOOL s p i f l a s h w r i t e m o d e = FALSE;
BOOL s p i f l a s h r e a d m o d e = FALSE;
BOOL f l a s h r d e n ;
76 BOOL new cfg = 1 ;
64 Matthias Zurbrügg, Christoph Zimmermann