Gecko3 - CCC Event Weblog

E. Quellcode
E.1. Firmware
E.1.1. Cypress Firmware Framwork
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// F i l e : fw . c
// Contents : Firmware frameworks t a s k d i s p a t c h e r and d e v i c e r e q u e s t p a r s e r
// source .
//
6 // i n d e n t 3 . NO TABS!
//
// $Revision : 17 $
// $Date : 11/15/01 5:45 p $
//
11 // Copyright ( c ) 2002 Cypress Semiconductor , Inc . A l l r i g h t s r e s e r v e d
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#include ” fx2 . h”
#include ” f x 2 r e g s . h”
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// Constants
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#define DELAY COUNT 0 x9248 ∗8L // Delay f o r 8 sec at 24Mhz , 4 sec at 48
#define IFREQ 48000 // IFCLK c o n s t a n t f o r S y n c h r o n i z a t i o n Delay
21 #define CFREQ 48000 // CLKOUT c o n s t a n t f o r S y n c h r o n i z a t i o n Delay
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// Random Macros
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26 #define min ( a , b ) ( ( ( a ) (b ) ) ?( a ) : ( b ) )
// R e g i s t e r s which r e q u i r e a s y n c h r o n i z a t i o n delay , see s e c t i o n 15.14
// FIFORESET FIFOPINPOLAR
31 // INPKTEND OUTPKTEND
// EPxBCH: L REVCTL
// GPIFTCB3 GPIFTCB2
// GPIFTCB1 GPIFTCB0
// EPxFIFOPFH: L EPxAUTOINLENH: L
36 // EPxFIFOCFG EPxGPIFFLGSEL
// PINFLAGSxx EPxFIFOIRQ
// EPxFIFOIE GPIFIRQ
// GPIFIE GPIFADRH: L
// UDMACRCH: L EPxGPIFTRIG
41 // GPIFTRIG
// Note : The pre−REVE EPxGPIFTCH/L r e g i s t e r are a f f e c t e d , as w e l l . . .
// . . . t h e s e have been r e p l a c e d by GPIFTC[ B3 : B0 ] r e g i s t e r s
46 #include ” f x 2 s d l y . h” // Define IFREQ and CFREQ above t h i s #i n c l u d e
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// Global V a r i a b l e s
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51 v o l a t i l e BOOL GotSUD ;
BOOL Rwuen ;
BOOL S e l f p w r ;
v o l a t i l e BOOL S l e e p ; // S l e e p mode e n a b l e f l a g
56 WORD pDeviceDscr ; // Pointer to Device D e s c r i p t o r ; D e s c r i p t o r s may be moved
WORD pDeviceQualDscr ;
WORD pHighSpeedConfigDscr ;
WORD pFullSpeedConfigDscr ;
WORD pConfigDscr ;
61 WORD pOtherConfigDscr ;
58 Matthias Zurbrügg, Christoph Zimmermann