Gecko3 - CCC Event Weblog
Gecko3 - CCC Event Weblog
Gecko3 - CCC Event Weblog
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F. Schemas<br />
FPGA Banks 0,2,4,6<br />
PWR_DOWN/INT<br />
fpga1<br />
fpga1.SchDoc<br />
LED[0..7]<br />
ETH_RESET<br />
D[0..15]<br />
D[0..15] INIT_B/WRX<br />
INIT_B/WRX<br />
Button[0..3]<br />
TX_CLK<br />
Dram_D1_[0..15] Dram_D1_[0..15] BUSY/RDYX<br />
BUSY/RDYX<br />
A A<br />
Dram_A1_[0..13] Dram_A1_[0..13]<br />
Switch[0..3]<br />
RXD_[0..3]<br />
Dram_LDM1 Dram_LDM1<br />
PKTEND<br />
Dram_UDM1 Dram_UDM1<br />
RX_CLK<br />
Dram_CS1<br />
Dram_CS1<br />
Dram_WE1<br />
Dram_WE1<br />
RX_DV<br />
Dram_CAS1 Dram_CAS1<br />
Dram_RAS1 Dram_RAS1<br />
RX_ER<br />
Dram_CKE1 Dram_CKE1<br />
Dram_CK1<br />
Dram_CK1<br />
CRS<br />
Dram_CK1<br />
Dram_CK1<br />
Dram_BA1_1 Dram_BA1_1<br />
COL<br />
Dram_BA1_0 Dram_BA1_0<br />
Dram_LDQS1 Dram_LDQS1<br />
1-Hz-Clock<br />
TX_EN<br />
Dram_UDQS1 Dram_UDQS1<br />
Dram_D0_[0..15] Dram_D0_[0..15]<br />
SSPEXTCLK<br />
TXD_[0..3]<br />
Dram_A0_[0..13] Dram_A0_[0..13]<br />
Dram_LDM0 Dram_LDM0<br />
SSPSYSCLK<br />
MDC<br />
Dram_UDM0 Dram_UDM0<br />
Dram_CS0<br />
Dram_CS0<br />
GPIO2[0..18]<br />
MDIO<br />
Dram_WE0<br />
Dram_WE0<br />
Dram_CAS0 Dram_CAS0<br />
DREQ[1..2]<br />
Dram_RAS0 Dram_RAS0<br />
Dram_CKE0 Dram_CKE0<br />
MD[0..31]<br />
Dram_CK0<br />
Dram_CK0<br />
Dram_CK0<br />
Dram_CK0<br />
MA[0..25]<br />
Dram_BA0_1 Dram_BA0_1<br />
2.5V I/O Bank needed<br />
Dram_BA0_0 Dram_BA0_0<br />
B DQM[0..3]<br />
Dram_LDQS0 Dram_LDQS0<br />
B<br />
Dram_UDQS0 Dram_UDQS0<br />
SDA<br />
Flash_A[0..23] Flash_A[0..23]<br />
Flash_A[0..23]<br />
SCL<br />
SSPSCLK<br />
SSPSFRM<br />
SSPTXD<br />
SSPRXD<br />
Flash_D0_[0..15]<br />
nOE<br />
nWE<br />
PWM[0..7]<br />
fpga2<br />
RDnWR<br />
fpga2.SCHDOC<br />
Encoder[0..7]<br />
Flash_D1_[0..15]<br />
nCS4<br />
D[0..15]<br />
D[0..15]<br />
Sensors[0..5]<br />
Flash_BYTE<br />
CS_B/RDYU<br />
CS_B/RDYU<br />
nCS3<br />
RDWR_B/WRU<br />
RDWR_B/WRU<br />
GPIO1_[0..5]<br />
Flash_WE<br />
EXTCLK0<br />
EXTCLK0<br />
nCS1<br />
EXTCLK1<br />
EXTCLK1<br />
Power Good<br />
Flash_RP<br />
Dram_D1_[0..15] Dram_D1_[0..15]<br />
RDY<br />
Dram_A1_[0..13] Dram_A1_[0..13]<br />
Low Battery<br />
Flash_OE<br />
Dram_LDM1 Dram_LDM1<br />
C FF_RXD<br />
Dram_UDM1 Dram_UDM1<br />
C<br />
Flash_CE0<br />
Dram_CS1<br />
Dram_CS1<br />
FF_CTS<br />
Dram_WE1<br />
Dram_WE1<br />
Dram_CAS1 Dram_CAS1<br />
FF_DCD<br />
Dram_RAS1 Dram_RAS1<br />
Dram_CKE1 Dram_CKE1<br />
FF_DSR<br />
Dram_CK1<br />
Dram_CK1<br />
Serial out<br />
Dram_CK1<br />
Dram_CK1<br />
MOSI<br />
FF_RI<br />
Dram_BA1_1 Dram_BA1_1<br />
Serial in<br />
Dram_BA1_0 Dram_BA1_0<br />
SCLK<br />
FF_RTS<br />
Dram_LDQS1 Dram_LDQS1<br />
Dram_UDQS1 Dram_UDQS1<br />
MISO<br />
FF_DTR<br />
Dram_D0_[0..15] Dram_D0_[0..15]<br />
Dram_A0_[0..13] Dram_A0_[0..13]<br />
SPI_CS_F<br />
FF_TXD<br />
Dram_LDM0 Dram_LDM0<br />
Dram_UDM0 Dram_UDM0<br />
Dram_CS0<br />
Dram_CS0<br />
Dram_WE0<br />
Dram_WE0<br />
Dram_CAS0 Dram_CAS0<br />
Dram_RAS0 Dram_RAS0<br />
Dram_CKE0 Dram_CKE0<br />
fpga-config<br />
Dram_CK0<br />
Dram_CK0<br />
fpga-config.SCHDOC<br />
Dram_CK0<br />
Dram_CK0<br />
PROG_B<br />
PROG_B<br />
DONE<br />
DONE<br />
Dram_BA0_1 Dram_BA0_1<br />
CCLK<br />
CCLK<br />
Dram_BA0_0 Dram_BA0_0<br />
Dram_LDQS0 Dram_LDQS0<br />
Dram_UDQS0 Dram_UDQS0<br />
TMS<br />
TMS<br />
D<br />
TCK<br />
TCK<br />
D<br />
TDO<br />
TDO<br />
FPGA Banks 1,3,5,7<br />
TDI<br />
TDI<br />
Berne School of Applied Science<br />
School of Engineering and<br />
Information Technology<br />
Quellgasse 21<br />
CH-2501 Biel<br />
Titel <strong>Gecko3</strong>: FPGA Parts<br />
Blattgrösse: A3 Nummer:<br />
Revision: 0.7<br />
Datum: 08.12.2006 Zeit: 15:17:53 Blatt von 18<br />
Datei: C:\Documents and Settings\ zimmc5\svn\fpga.SCHDOC<br />
Abbildung F.2.: FPGA Blockdiagramm<br />
124 Christoph Zimmermann
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