Gecko3 - CCC Event Weblog

E.2. Loopback Core
106
end i f ;
end i f ;
end process ;
end B e h a v i o r a l ;
E.2.3. Statemachine
−− C: \DOCUMENTS AND SETTINGS\ZIMMC5\GECKO3 LOOPBACK\STM. vhd
2 −− VHDL code c r e a t e d by Xilinx ’ s StateCAD 8.2 i
−− Fri Dec 08 1 0 : 4 9 : 1 1 2006
−− This VHDL code ( f o r use with X i l i n x XST) was generated using :
−− enumerated s t a t e assignment with s t r u c t u r e d code format .
7 −− Minimization i s enabled , i m p l i e d e l s e i s enabled ,
−− and o u t p u t s are speed o p t i m i z e d .
LIBRARY i e e e ;
USE i e e e . s t d l o g i c 1 1 6 4 . a l l ;
12
ENTITY STM IS
PORT (CLK,RDYU,RESET,WRU, z e r o : IN s t d l o g i c ;
down ,RDYX, up , we , writeEN ,WRX : OUT s t d l o g i c ) ;
END;
17
ARCHITECTURE BEHAVIOR OF STM IS
TYPE t y p e s r e g IS (ADRESS UP,CHECK END,CHECK WRU,END PACKET,GET REQUEST, IDLE
,PKTEND,SAVE DATA,SEND DATA,SEND REQUEST,VALID DATA,WAIT END) ;
SIGNAL sreg , n e x t s r e g : t y p e s r e g ;
22 SIGNAL next down , next RDYX , next up , next we , next writeEN , next WRX :
s t d l o g i c ;
BEGIN
PROCESS (CLK, RESET, n e x t s r e g , next down , next RDYX , next up , next we ,
next writeEN , next WRX)
27 BEGIN
IF ( RESET= ’1 ’ ) THEN
s r e g