Gecko3 - CCC Event Weblog

E. Quellcode
) ;
41 end datapath ;
architecture B e h a v i o r a l of datapath i s
signal NOT writeEN : s t d l o g i c ;
46 signal ADDR: s t d l o g i c v e c t o r (8 downto 0) ;
signal t r a s h : s t d l o g i c v e c t o r (15 downto 0) ;
signal trashp : s t d l o g i c v e c t o r (3 downto 0) ;
signal DI : s t d l o g i c v e c t o r (15 downto 0) ;
signal DO: s t d l o g i c v e c t o r (15 downto 0) ;
51
begin
NOT writeEN X” 000000000 ” , −− Ouput v a l u e upon SSR a s s e r t i o n
66 WRITE MODE => ”WRITE FIRST” −− WRITE FIRST, READ FIRST or NO CHANGE
)
port map (
DO(31 downto 16) => trash , −− 32− b i t Data Output
DO(15 downto 0) => DO,
71 DOP => trashp , −− 4− b i t p a r i t y Output
ADDR => ADDR, −− 9− b i t Address Input
CLK => clk , −− Clock
DI (31 downto 16) => ” 0000000000000000 ” , −− 32− b i t Data Input
DI (15 downto 0) => DI ,
76 −− DI(15 downto 0) => DATA,
DIP => ” 0000 ” , −− 4− b i t p a r i t y Input
EN => ’ 1 ’ , −− RAM Enable Input
SSR => ’ 0 ’ , −− Synchronous Set / Reset Input
WE => we −− Write Enable Input
81 ) ;
−− End o f RAMB16 S36 inst i n s t a n t i a t i o n
IOBUFFER:
86 for i in 15 downto 0 generate
begin
iod : IOBUF
port map (
I => DO( i ) ,
91 ) ;
end generate ;
process ( clk , r e s e t )
begin
96 i f r e s e t = ’1 ’ then
ADDR ’0 ’) ;
e l s i f c l k = ’1 ’ and clk ’ event then
i f up= ’1 ’ then
ADDR DI ( i ) , T => NOT writeEN
98 Matthias Zurbrügg, Christoph Zimmermann