Gecko3 - CCC Event Weblog

E.2. Loopback Core
WRUint WRX, RDYU => RDYUint , RDYX =>
RDYX,
z e r o => zero , writeEN => writeEN , we => we , up => up , down => down
) ;
i d a t a p a t h : datapath
port map(
90 c l k => CLK, r e s e t => RESET, z e r o => zero , we => we , up => up , down => down ,
writeEN => writeEN , data => DATA
) ;
end B e h a v i o r a l ;
E.2.2. Datenpfad
1 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
−− Diplomwork :
−− Gecko3 SoC HW/SW Development Board
−−
−− ( ‘ \ ( ) ( ) ( )
6 −− | ( ) ) | ( | | | | Berne U n i v e r s i t y o f Applied S c i e n c e s
−− | < ’| ) | | School o f Engineering and
−− | ( ) ) | | | | | | Information Technology
−− ( / ’( ) ( ) ( )
−−
11 −−
−− Author : Christoph Zimmermann
−− Date o f c r e a t i o n : 8.11.2006
−− D e s c r i p t i o n :
−− Datapath f o r t h e l o o p b a c k module
16 −−
−− Target Devices : X i l i n x Spartan3 FPGA’ s ( usage o f BlockRam in t h e Datapath )
−− Tool v e r s i o n s : 8.2 i
−− Dependencies :
−−
21 −−
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
library IEEE ;
use IEEE . STD LOGIC 1164 .ALL;
26 use IEEE . STD LOGIC ARITH .ALL;
use IEEE . STD LOGIC UNSIGNED .ALL;
−−−− Uncomment t h e f o l l o w i n g l i b r a r y d e c l a r a t i o n i f i n s t a n t i a t i n g
−−−− any X i l i n x p r i m i t i v e s in t h i s code .
31 library UNISIM ;
use UNISIM . VComponents . a l l ;
entity datapath i s
port (
36 clk , r e s e t , we , up , down , writeEN : IN s t d l o g i c ;
z e r o : OUT s t d l o g i c ;
data : inout s t d l o g i c v e c t o r (15 downto 0)
Project Report 97