Gecko3 - CCC Event Weblog

E. Quellcode
−− | ( ) ) | | | | | | Information Technology
−− ( / ’( ) ( ) ( )
10 −−
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−− Author : Christoph Zimmermann
−− Date o f c r e a t i o n : 8.11.2006
−− D e s c r i p t i o n :
15 −− FPGA Module to t e s t t h e communication between t h e EZ−USB and t h e FPGA.
−− The EZ−USB sends data (16 b i t wide ) to t h e FPGA. t he y are s t o r e d and when
−− t h e s e l e c t e d number o f data ( s e l e c t e d by t h e s w i t c h e s ) i s reached t h e FPGA
−− s t a r t s to send back t h e data to t h e EZ−USB in r e v e r s e d order (FILO)
−−
20 −− Target Devices : X i l i n x Spartan3 FPGA’ s ( usage o f BlockRam in t h e Datapath )
−− Tool v e r s i o n s : 8.2 i
−− Dependencies :
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−−
25 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
library IEEE ;
use IEEE . STD LOGIC 1164 .ALL;
use IEEE . STD LOGIC ARITH .ALL;
30 use IEEE . STD LOGIC UNSIGNED .ALL;
−−−− Uncomment t h e f o l l o w i n g l i b r a r y d e c l a r a t i o n i f i n s t a n t i a t i n g
−−−− any X i l i n x p r i m i t i v e s in t h i s code .
library UNISIM ;
35 use UNISIM . VComponents . a l l ;
entity loopback i s
port (
DATA: inout s t d l o g i c v e c t o r (15 downto 0) ;
40 CLK, RESET, WRU, RDYU: in s t d l o g i c ; −−r e s e t b u t t o n on development board i s 1
when p r e s s e d
WRX, RDYX, PW: out s t d l o g i c
) ;
end loopback ;
45 architecture B e h a v i o r a l of loopback i s
signal up , down , zero , writeEN , we : s t d l o g i c ;
signal WRUint , RDYUint : s t d l o g i c ;
50 component STM
PORT (
CLK, RDYU, RESET, WRU, z e r o : IN s t d l o g i c ;
down , RDYX, up , we , writeEN , WRX : OUT s t d l o g i c
) ;
55 end component ;
component datapath
port (
clk , r e s e t , we , up , down , writeEN : IN s t d l o g i c ;
60 z e r o : OUT s t d l o g i c ;
data : inout s t d l o g i c v e c t o r (15 downto 0)
) ;
end component ;
65 begin
PW